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| STM8L151xx, STM8L152xx 8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators Preliminary data Features Operating conditions - Operating power supply range 1.8 V to 3.6 V (down to 1.65 V at power down) - Temperature range: - 40 C to 85 or 125 C Low power features - 5 low power modes: Wait , Low power run (5.4 A), Low power wait (3 A), Active-halt with RTC (1 A), Halt (400 nA) - Dynamic consumption: 192 A/MHz - Ultralow leakage per I/0: 50 nA - Fast wakeup from Halt: 5 s Advanced STM8 core - Harvard architecture and 3-stage pipeline - Max freq. 16 MHz, 16 CISC MIPS peak - Up to 40 external interrupt sources Reset and supply management - Low power, ultrasafe BOR reset with 5 selectable thresholds - Ultralow power POR/PDR - Programmable voltage detector (PVD) Clock management - 1 to 16 MHz crystal oscillator - 32 kHz crystal oscillator - Internal 16 MHz factory-trimmed RC - Internal 38 kHz low consumption RC - Clock security system Low power RTC - BCD calendar with alarm interrupt - Auto-wakeup from Halt w/ periodic interrupt LCD: up to 4x28 segments w/ step-up converter Memories - Up to 32 KB of Flash program memory and 1 Kbyte of data EEPROM with ECC, RWW - Flexible write and read protection modes - Up to 2 Kbytes of RAM DMA - 4 channels; supported peripherals: ADC, DAC, SPI, I2C, USART, timers - 1 channel for memory-to-memory 12-bit DAC with output buffer LQFP48 VFQFPN48 WFQFPN32 LQFP32 WFQFPN28 12-bit ADC up to 1 Msps/25 channels - T. sensor and internal reference voltage 2 Ultralow power comparators - 1 with fixed threshold and 1 rail to rail - Wakeup capability Timers - Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder - One 16-bit advanced control timer with 3 channels, supporting motor control - One 8-bit timer with 7-bit prescaler - 2 watchdogs: 1 Window, 1 Independent - Beeper timer with 1, 2 or 4 kHz frequencies Communication interfaces - Synchronous serial interface (SPI) - Fast I2C 400 kHz SMBus and PMBus - USART (ISO 7816 interface and IrDA) Up to 41 I/Os, all mappable on interrupt vectors Up to 16 capacitive sensing channels with free firmware Development support - Fast on-chip programming and non intrusive debugging with SWIM - Bootloader using USART 96-bit unique ID Device summary Part number STM8L151C6, STM8L151C4, STM8L151K6, STM8L151K4, STM8L151G6, STM8L151G4 STM8L152C6, STM8L152C4, STM8L152K6, STM8L152K4 Table 1. Reference STM8L151xx (without LCD) STM8L152xx (with LCD) September 2009 Doc ID 15962 Rev 2 1/101 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STM8L151xx, STM8L152xx Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 3.2.2 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 3.3.2 3.3.3 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System configuration controller and routing interface . . . . . . . . . . . . . . . 19 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13.1 3.13.2 3.13.3 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 3.14.2 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Contents 3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.16.1 3.16.2 3.16.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17 3.18 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 5.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 7 8 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 8.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 59 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Doc ID 15962 Rev 2 3/101 Contents 8.3.11 8.3.12 8.3.13 8.3.14 STM8L151xx, STM8L152xx Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.1 9.2 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10 11 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8L15x low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 10 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM8L15x pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 65 Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Total current consumption and timing in Halt mode at VDD = 2 V . . . . . . . . . . . . . . . . . . 67 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 75 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DAC characteristics, output on PF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Doc ID 15962 Rev 2 5/101 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. STM8L151xx, STM8L152xx ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP32 - 32-pin low profile quad flat package, package mechanical data . . . . . . . . . . . . 96 VFQFPN48 - very thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP48 - 48-pin low profile quad flat package (7x7), package mechanical data . . . . . . . 98 6/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. STM8L15xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM8L15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM8L151Gx 28-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM8L151Kx 32-pin package pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM8L152Kx 32-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM8L151Cx 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM8L152Cx 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 88 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 89 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) . 94 Recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP32 - 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP48 - 48-pin low profile quad flat package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . . 98 STM8L15xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Doc ID 15962 Rev 2 7/101 Introduction STM8L151xx, STM8L152xx 1 Introduction This document describes the STM8L15xxx family features, pinout, mechanical data and ordering information. For more details on the whole STMicroelectronics Ultralow power family please refer to Section 2.2: Ultralow power continuum on page 11. The reference manual and Flash programming manuals will be available soon. For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). 2 Description The STM8L15xxx devices are members of the STM8L Ultralow power 8-bit family. They are referred to as medium-density devices in the STM8L15xxx reference manual (RM0031) and in the STM8L Flash programming manual (PM0054). They provide the following benefits: Integrated system - - - - Up to 32 Kbytes of medium-density embedded Flash program memory 1 Kbyte of data EEPROM Internal high speed and low-power low speed RC. Embedded reset 192 A/MHZ (dynamic consumption) 1 A in Active-halt mode Clock gated system and optimized power management Capability to execute from RAM for Low power wait mode and Low power run mode Up to 16 MIPS at 16 MHz CPU clock frequency Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access. Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. Wide choice of development tools Ultralow power consumption - - - - Advanced features - - Short development cycles - - The STM8L15xxx family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is available in the -40 to +85 C and -40 to +125 C temperature ranges. The STM8L15xxx Ultralow power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of 8/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Description a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultrafast Flash programming. All STM8L15xxx microcontrollers feature embedded data EEPROM and low power lowvoltage single-supply program Flash memory. The STM8L15xxx family 8-bit microcontrollers incorporate an extensive range of enhanced I/Os and peripherals. All devices offer 12-bit ADC, DAC, two comparators, Real-time clock three 16-bit timers, one 8-bit timer as well as standard communication interface such as SPI, I2C and USART. A 4x28-segment LCD is available on the STM8L152xx line. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. These features make the STM8L15xxx microcontroller family suitable for a wide range of applications: Medical and handheld equipment Application control and user interface PC peripherals, gaming, GPS and sport equipment Alarm systems, wired and wireless sensors Figure 1 on page 12 shows the general block diagram of the device family. Six different packages are proposed from 28 to 48 pins. Depending on the device chosen, different sets of peripherals are included. Section 3 on page 12 gives an overview of the complete range of peripherals proposed in this family. All STM8L Ultralow power products are based on the same architecture with the same memory mapping and a coherent pinout. Doc ID 15962 Rev 2 9/101 Description STM8L151xx, STM8L152xx 2.1 Table 2. Device overview STM8L15x low power device features and peripheral counts Features STM8L151Gx 16 32 STM8L15xKx 16 1 2 No Basic 1 (8-bit) 2 (16-bit) 1 (16-bit) 1 1 1 26 (3) STM8L15xCx 16 32 Flash (Kbytes) Data EEPROM (Kbytes) RAM-Kbytes LCD 32 2 4x17 (1) 2 4x28 (1) 1 (8-bit) 2 (16-bit) 1 (16-bit) 1 1 1 (1)(3) 1 (8-bit) 2 (16-bit) 1 (16-bit) 1 1 1 30 (2)(3) Timers General purpose Advanced control SPI Communication I2C interfaces USART GPIOs 12-bit synchronized ADC (number of channels) 12-Bit DAC (number of channels) Comparators COMP1/COMP2 Others CPU frequency Operating voltage Operating temperature Packages 1. STM8L152xx versions only 2. STM8L151xx versions only or 29 41(3) 1 (25) 1 (1) 2 1 (18) 1 (1) 2 1 (22 (2) or 21 (1)) 1 (1) 2 RTC, window watchdog, independent watchdog, 16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator 16 MHz 1.8 V to 3.6 V (down to 1.65 V at power down) -40 to +85 C / -40 to +125 C WFQFPN28 (4)(4x4; 0.8 mm thickness) WFQFPN32 (5)(5x5; 0.8 mm thickness) LQFP32(7x7) VFQFPN48 (6)(4x4; 1 mm thickness) LQFP48 3. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1). 4. WFQFPN28 package used in the sampling phase. In the production phase, the UFQFPN28 package will be used with a thickness equal to 0.6 mm. 5. WFQFPN32 package used in the sampling phase. In the production phase, the UFQFPN32 package will be used with a thickness equal to 0.6 mm. 6. VFQFPN48 package used in the sampling phase. In the production phase, the UFQFPN48 package will be used with a thickness equal to 0.6 mm. 10/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Description 2.2 Ultralow power continuum The Ultralow power STM8L151xx and STM8L152xx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers UtraLowPower strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.13 m ultralow leakage process. Note: 1 2 The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices. The STM32L family is pin-to-pin compatible with the general purpose STM32F family. Please refer to STM32L15x documentation for more information on these devices. Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM CortexTM-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the Ultralow power performance to range from 5 up to 33.3 DMIPs. Shared peripherals STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy migration from one family to another: Analog peripherals: ADC1, DAC, and comparators COMP1/COMP2 Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L151xx/152xx and STM32L15xx devices use a common architecture: Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down Architecture optimized to reach ultralow consumption both in low power modes and Run mode Fast startup strategy from low power modes Flexible system clock Ultrasafe reset: same reset strategy for both STM8L15xxx and STM32L15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector. Features ST UtraLowPower continuum also lies in feature compatibility: More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm Memory density ranging from 4 to 128 Kbytes Doc ID 15962 Rev 2 11/101 Functional overview STM8L151xx, STM8L152xx 3 Figure 1. Functional overview STM8L15xxx device block diagram OSC_IN, OSC_OUT 1-16 MHz oscillator 16 MHz internal RC Clock controller and CSS @VDD VDD18 Power VOLT. REG. VSS VDD =1.65 V to 3.6 V OSC32_IN, OSC32_OUT 32 kHz oscillator 38 kHz internal RC Interrupt controller STM8 Core Clocks to core and peripherals RESET POR/PDR BOR PVD NRST SWIM 2 channels 2 channels 3 channels Debug module (SWIM) 16-bit Timer 2 16-bit Timer 3 16-bit Timer 1 8-bit Timer 4 Address, control and data buses PVD_IN 32 Kbytes Program memory 1 Kbyte Data EEPROM 2 Kbytes RAM IR_TIM Infrared interface DMA1 (4 channels) Port A Port B Port C Port D Port E Port F Beeper RTC IWDG (38 kHz clock) WWDG PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF0 SCL, SDA, SMB MOSI, MISO, SCK, NSS RX, TX, CK IC1 SPI1 USART1 @VDDA/VSSA VDDA VSSA ADC1_INx VDDREF VSSREF 12-bit ADC1 Temp sensor Internal reference voltage COMP 1 COMP 2 12-bit DAC 12-bit DAC LCD booster BEEP ALARM, CALIB VREFINT out COMP1_INP COMP2_INP COMP2_INM DAC_OUT VDDREF VSSREF VLCD = 2.5 V to 3.6 V LCD driver 4x28 SEGx, COMx 1. Legend: ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access DAC: Digital-to-analog converter IC: Inter-integrated circuit multimaster interface IWDG: Independent watchdog LCD: Liquid crystal display POR/PDR: Power on reset / power down reset RTC: Real-time clock SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog 12/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Functional overview 3.1 Low power modes The STM8L15xxx supports five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Wait consumption is around 350 A. Low power run mode: CPU clock runs. Flash, data EEPROM, voltage regulator and all peripherals are stopped except RTC and one other peripheral which can remain active (ex: one timer). Execution is done from RAM with a low speed oscillator (LSI or LSE). The microcontroller enters Low power run mode by software and can exit from this mode by software or by a Reset. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power run mode consumption is around 5.4 A (peripherals OFF). Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power wait mode consumption is around 3 A (peripherals OFF). Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. Active-halt consumption with RTC on LSI is 0.9 A. Active-halt consumption with RTC on LSE is 1 A. Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 6 s. Halt consumption is 400 nA. Dynamic consumption in run mode is 190 A/MHz. 3.2 3.2.1 Central processing unit STM8 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. Architecture and registers Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without Doc ID 15962 Rev 2 13/101 Functional overview offset and read-modify-write type data manipulations STM8L151xx, STM8L152xx 8-bit accumulator 24-bit program counter - 16 Mbyte linear memory space 16-bit stack pointer - access to a 64 Kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes Indexed indirect addressing mode for lookup tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers 3.2.2 Interrupt controller The STM8L15xxx features a nested vectored interrupt controller: Nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority Up to 40 external interrupt sources on 11 vectors Trap and reset interrupts 14/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Functional overview 3.3 3.3.1 Reset and supply management Power supply scheme The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: VSS ; VDD = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for I/Os and for the internal regulator. Provided externally through VDD pins, the corresponding ground pin is VSS. VSSA ; VDDA = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for analog peripherals (minimum voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VSSIO ; VDDIO = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for I/Os. VDDIO and VSSIO must be connected to VDD and VSS, respectively. VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided externally through VREF+ and VREF- pin. VREF+ (for DAC): external voltage reference for DAC must be provided externally through VREF+. 3.3.2 Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD min value at power down is 1.65 V). Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains in reset state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The STM8L15xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes. Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low power wait modes. Doc ID 15962 Rev 2 15/101 Functional overview STM8L151xx, STM8L152xx When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.4 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. System clock sources: 4 different clock sources can be used to drive the system clock: - - - - 1-16 MHz High speed external crystal (HSE) 16 MHz High speed internal RC oscillator (HSI) 32.768 Low speed external crystal (LSE) 38 kHz Low speed internal RC (LSI) RTC and LCD clock sources: the above four sources can be chosen to clock the RTC and the LCD, whatever the system clock. Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI. Configurable main clock output (CCO): This outputs an external clock for use by the application. 16/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Figure 2. STM8L15x clock tree diagram Functional overview 3.5 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours Periodic alarms based on the calendar can also be generated from every second to every year Active-halt consumption with LSI and Auto-wakeup: 0.9 A Active-halt consumption with LSE, calendar and auto-wakeup: 1 A Doc ID 15962 Rev 2 17/101 Functional overview STM8L151xx, STM8L152xx 3.6 LCD (Liquid crystal display) The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels. Internal step-up converter to guarantee contrast control whatever VDD. Static 1/2, 1/3, 1/4 duty supported. Static 1/2, 1/3 bias supported. Phase inversion to reduce power consumption and EMI. Up to 4 pixels which can programmed to blink. The LCD controller can operate in Halt mode. Note: Unnecessary segments and common pins can be used as general I/O pins. 3.7 Memories The STM8L15xxx devices have the following main features: Up to 2 Kbytes of RAM The non-volatile memory is divided into three arrays: - - - Up to 32 Kbytes of medium-density embedded Flash program memory 1 Kbyte of Data EEPROM Option bytes. The EEPROM embeds the error correction code (ECC) feature. It supports the read-whilewrite (RWW): it is possible to execute the code from the program matrix while programming/erasing the data matrix. The option byte protects part of the Flash program memory from write and readout piracy. 3.8 DMA A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, DAC, I2C1, SPI1, USART1, the 4 Timers. 3.9 Analog-to-digital converter 12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel), temperature sensor and internal reference voltage Conversion time down to 1 s with fSYSCLK= 16 MHz Programmable resolution Programmable sampling time Single and continuous mode of conversion Scan capability: automatic conversion performed on a selected group of analog inputs Analog watchdog Triggered by timer Note: ADC1 can be served by DMA1. 18/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Functional overview 3.10 Digital-to-analog converter (DAC) 12-bit DAC with output buffer Synchronized update capability using TIM4 DMA capability External triggers for conversion Input reference voltage VREF+ for better resolution Note: DAC can be served by DMA1. 3.11 Ultralow power comparators The STM8L15x embeds two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal or external (coming from an I/O). One comparator with fixed threshold (COMP1). One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one of the following: - - - DAC output External I/O Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4) The two comparators can be used together to offer a window function. They can wake up from Halt mode. 3.12 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface allows application software to control the routing of different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1, COMP2, DAC and the internal reference voltage VREFINT. Finally, it provides a set of registers for efficiently managing a set of dedicated I/Os supporting up to 16 capacitive sensing channels using the ProxSenseTM technology. 3.13 Timers STM8L15xxx devices contain one advanced control timer (TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). All the timers can be served by DMA1. Table 3 compares the features of the advanced control, general-purpose and basic timers. Doc ID 15962 Rev 2 19/101 Functional overview Table 3. Timer STM8L151xx, STM8L152xx Timer feature comparison Prescaler factor Any integer from 1 to 65536 16-bit up/down Any power of 2 from 1 to 128 8-bit up Any power of 2 from 1 to 32768 Yes 2 None 0 DMA1 request generation Capture/compare channels 3+1 Complementary outputs 3 Counter Counter resolution type TIM1 TIM2 TIM3 TIM4 3.13.1 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver. 16-bit up, down and up/down autoreload counter with 16-bit prescaler 3 independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output 1 additional capture/compare channel which is not connected to an external I/O Synchronization module to control the timer with external signals Break input to force timer outputs into a defined state 3 complementary outputs with adjustable dead time Encoder mode Interrupt capability on various events (capture, compare, overflow, break, trigger) 3.13.2 16-bit general purpose timers 16-bit autoreload (AR) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1...128) 2 individually configurable capture/compare channels PWM mode Interrupt capability on various events (capture, compare, overflow, break, trigger) Synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.13.3 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow or for DAC trigger generation. 20/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Functional overview 3.14 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. 3.14.1 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.14.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure. 3.15 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 3.16 3.16.1 Communication interfaces SPI The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices. Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on 2 lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software Hardware CRC calculation Slave/master selection input pin Note: SPI1 can be served by the DMA1 Controller. 3.16.2 IC The I2C bus interface (I2C1) provides multi-master capability, and controls all IC busspecific sequencing, protocol, arbitration and timing. Master, slave and multi-master capability Standard mode up to 100 kHz and fast speed modes up to 400 kHz. 7-bit and 10-bit addressing modes. SMBus 2.0 and PMBus support Hardware CRC calculation Doc ID 15962 Rev 2 21/101 Functional overview Note: I2C1 can be served by the DMA1 Controller. STM8L151xx, STM8L152xx 3.16.3 USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 1 Mbit/s full duplex SCI SPI1 emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.17 Infrared (IR) interface The STM8L15x devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.18 Development support Development tools Development tools for the STM8 microcontrollers include: The STice emulation system offering tracing and code profiling The STVD high-level language debugger including C compiler, assembler and integrated development environment The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers. Bootloader A bootloader is available to reprogram the Flash memory using the USART1 interface. 22/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Pin description 4 Pin description Figure 3. STM8L151Gx 28-pin package pinout PC6 PC5 PC4 PC3 PC2 23 28 27 26 25 24 NRST/PA1 PA2 PA3 PA4 PA5 VSS/VSSA/VREFVDD/VDDA/VREF+ PC1 22 21 20 19 18 17 16 15 PA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC0 PD4 PB7 PB6 PB5 PB4 PB3 PD0 PD1 PD2 PD3 PB0 PB1 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 Figure 4. STM8L151Kx 32-pin package pinout (without LCD) PA0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 32 31 30 29 28 27 26 25 NRST/PA1 PA2 PA3 PA4 PA5 PA6 VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package. Figure 5. STM8L152Kx 32-pin package pinout (with LCD) PA0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 32 31 30 29 28 27 26 25 PD0 PD1 PD2 PD3 PB0 PB1 PB2 PB3 NRST/PA1 PA2 PA3 PA4 PA5 PA6 VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package. Doc ID 15962 Rev 2 VLCD PD1 PD2 PD3 PB0 PB1 PB2 PB3 PB2 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 23/101 Pin description Figure 6. STM8L151Cx 48-pin pinout (without LCD) PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSSIO VDDIO PC1 PC0 STM8L151xx, STM8L152xx PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS/VSSA/VREFVDD VDDA VREF+ 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PD7 PD6 PD5 PD4 PF0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 1. Reserved. Must be tied to VDD. Figure 7. STM8L152Cx 48-pin pinout (with LCD) PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSSIO VDDIO PC1 PC0 PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS/VSSA/VREFVDD VDDA VREF+ 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 Res. (1) PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 PB0 PD7 PD6 PD5 PD4 PF0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 24/101 Doc ID 15962 Rev 2 VLCD PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 PB0 STM8L151xx, STM8L152xx Legend / Abbreviations for Table 4: Type: I/O level: Input level: Output level: Pin description I = input, O = output, S = power supply FT = 5 V tolerant CM = CMOS HS = High sink/source (20 mA) float = floating, wpu = weak pull-up T= true open drain, OD = open drain, PP = push-pull Port and control configuration: Input: Output: Reset state is shown in bold. Table 4. Pin number VFQFPN48 and LQFP48 STM8L15x pin description Input Output Main function (after reset) High sink/source I/O level Ext. interrupt WFQFPN28 WFQFPN32 Type floating Pin name Default alternate function wpu OD 2 3 1 2 1 NRST/PA1(1) PA2/OSC_IN/ 2 [USART1_TX](3)/ [SPI1_MISO] (3) 3 I/O I/O X X X HS X HS X X Reset PP PA1 HSE oscillator input / [USART1 X Port A2 transmit] / [SPI1 master in- slave out] / HSE oscillator output / [USART1 X Port A3 receive]/ [SPI1 master out/slave in]/ Timer 2 - break input / X Port A4 LCD COM 0 / ADC1 input 2 / Comparator 1 positive input Timer 2 - break input / [Timer 2 - trigger] / LCD_COM 0 / X Port A4 ADC1 input 2 / Comparator 1 positive input Timer 3 - break input / X Port A5 LCD_COM 1 / ADC1 input 1/ Comparator 1 positive input Timer 3 - break input / [Timer 3 trigger] / LCD_COM 1 / X Port A5 ADC1 input 1 / Comparator 1 positive input [ADC1 - trigger] / LCD_COM2 / X Port A6 ADC1 input 0 / Comparator 1 positive input 4 3 PA3/OSC_OUT/[USART1 I/O _RX](3)/[SPI1_MOSI](3) X X X HS X 5 - PA4/TIM2_BKIN/ - LCD_COM0(2)/ADC1_IN2/ I/O COMP1_INP PA4/TIM2_BKIN/ [TIM2_TRIG](3)/ 4 LCD_COM0(2)/ ADC1_IN2/COMP1_INP X X X HS X - 4 I/O X X X HS X 6 - PA5/TIM3_BKIN/ LCD_COM1(2)/ADC1_IN1/ I/O COMP1_INP PA5/TIM3_BKIN/ [TIM3_TRIG](3)/ 5 I/O LCD_COM1(2)/ADC1_IN1/ COMP1_INP PA6/[ADC1_TRIG](3)/ - LCD_COM2(2)/ADC1_IN0/ I/O COMP1_INP X X X HS X - 5 X X X HS X 7 6 X X X HS X Doc ID 15962 Rev 2 25/101 Pin description Table 4. Pin number VFQFPN48 and LQFP48 STM8L151xx, STM8L152xx STM8L15x pin description (continued) Input Output Main function (after reset) High sink/source I/O level Ext. interrupt WFQFPN28 WFQFPN32 Type floating Pin name Default alternate function wpu OD 8 - - PA7/LCD_SEG0(2) I/O FT X X X X X X HS X HS X X Port A7 LCD segment 0 Timer 2 - channel 1 / LCD X Port B0 segment 10 / ADC1_IN18 / Comparator 1 positive input Timer 3 - channel 1 / LCD X Port B1 segment 11 / ADC1_IN17 / Comparator 1 positive input Timer 2 - channel 2 / LCD X Port B2 segment 12 / ADC1_IN16/ Comparator 1 positive input Timer 2 - trigger / LCD segment X Port B3 13 /ADC1_IN15 / Comparator 1 positive input [Timer 2 - trigger] / Timer 1 inverted channel 2 / LCD X Port B3 segment 13 / ADC1_IN15 / Comparator 1 positive input [Timer 2 - trigger] / Timer 1 inverted channel 1/ LCD segment X Port B3 13 / ADC1_IN15 / RTC alarm/ Comparator 1 positive input [SPI1 master/slave select] / LCD X Port B4 segment 14 / ADC1_IN14 / Comparator 1 positive input [SPI1 master/slave select] / LCD segment 14 / ADC1_IN14 / X Port B4 DAC output / Comparator 1 positive input [SPI1 clock] / LCD segment 15 / X Port B5 ADC1_IN13 / Comparator 1 positive input [SPI1 clock] / LCD segment 15 / X Port B5 ADC1_IN13 / DAC output/ Comparator 1 positive input PB0/TIM2_CH1/ I/O 24 13 12 LCD_SEG10(2)/ ADC1_IN18/COMP1_INP PB1/TIM3_CH1/ 25 14 13 LCD_SEG11(2)/ I/O ADC1_IN17/COMP1_INP PB2/ TIM2_CH2/ 26 15 14 LCD_SEG12(2)/ I/O ADC1_IN16/COMP1_INP 27 PB3/TIM2_TRIG/ - LCD_SEG13(2)/ I/O ADC1_IN15/COMP1_INP PB3/[TIM2_TRIG](3)/ TIM1_CH2N/LCD_SEG13 - (2) I/O /ADC1_IN15/ COMP1_INP PB3/[TIM2_TRIG](3)/ TIM1_CH1N/ I/O 15 LCD_SEG13(2)/ ADC1_IN15/RTC_ALARM /COMP1_INP PB4/[SPI1_NSS](3)/ - LCD_SEG14(2)/ I/O ADC1_IN14/COMP1_INP X X X HS X X X X HS X X X X HS X - 16 X X X HS X - - X X X HS X 28 - X X X HS X - PB4/[SPI1_NSS](3)/ LCD_SEG14(2)/ 17 16 ADC1_IN14/ COMP1_INP/DAC_OUT - I/O X X X HS X 29 PB5/[SPI1_SCK](3)/ I/O - LCD_SEG15(2)/ ADC1_IN13/COMP1_INP X X X HS X - PB5/[SPI1_SCK](3)/ LCD_SEG15(2)/ 18 17 ADC1_IN13/DAC_OUT/ COMP1_INP I/O X X X HS X 26/101 Doc ID 15962 Rev 2 PP STM8L151xx, STM8L152xx Table 4. Pin number VFQFPN48 and LQFP48 Pin description STM8L15x pin description (continued) Input Output Main function (after reset) High sink/source I/O level Ext. interrupt WFQFPN28 WFQFPN32 Type floating Pin name Default alternate function wpu OD T(4) T(4) 30 - PB6/[SPI1_MOSI](3)/ - LCD_SEG16(2)/ I/O ADC1_IN12/COMP1_INP X X X HS X [SPI1 master out/slave in]/ X Port B6 LCD segment 16 / ADC1_IN12 / Comparator 1 positive input [SPI1 master out]/ slave in / LCD segment 16 / X Port B6 ADC1_IN12 / DAC output / Comparator 1 positive input [SPI1 master in- slave out] / X Port B7 LCD segment 17 / ADC1_IN11 / Comparator 1 positive input Port C0 I2C1 data Port C1 I2C1 clock [USART1 receive] / LCD segment 22 / ADC1_IN6 / X Port C2 Comparator 1 positive input / Voltage reference output [USART1 transmit] / LCD segment 23 / ADC1_IN5 / X Port C3 Comparator 1 positive input / Comparator 2 negative input [USART1 synchronous clock] / I2C1_SMB / Configurable clock output / LCD segment 24 / X Port C4 ADC1_IN4 / Comparator 2 negative input / Comparator 1 positive input LSE oscillator input / [SPI1 X Port C5 master/slave select] / [USART1 transmit] X Port C6 LSE oscillator output / [SPI1 clock] / [USART1 receive] - PB6/[SPI1_MOSI](3)/ LCD_SEG16(2)/ 19 18 I/O ADC1_IN12/COMP1_INP/ DAC_OUT X X X HS X PB7/[SPI1_MISO](3)/ I/O 31 20 19 LCD_SEG17(2)/ ADC1_IN11/COMP1_INP 37 25 21 PC0/I2C1_SDA 38 26 22 PC1/I2C1_SCL I/O FT I/O FT X X X X X X X HS X PC2/[USART1_RX](3)/ 41 27 23 LCD_SEG22/ADC1_IN6/ I/O COMP1_INP/VREF_OUT PC3/[USART1_TX](3)/ LCD_SEG23(2)/ 42 28 24 ADC1_IN5/COMP1_INP/ COMP2_INM X X X HS X I/O X X X HS X PC4/[USART1_CK](3)/ I2C1_SMB/CCO/ I/O 43 29 25 LCD_SEG24(2)/ ADC1_IN4/COMP2_INM/ COMP1_INP PC5/OSC32_IN 44 30 26 /[SPI1_NSS](3)/ [USART1_TX](3) PC6/OSC32_OUT/ 45 31 27 [SPI1_SCK](3)/ [USART1_RX](3) 46 - X X X HS X I/O X X X HS X I/O X X X HS X PC7/LCD_SEG25(2)/ - ADC1_IN3/COMP2_INM/ I/O COMP1_INP X X X HS X LCD segment 25 /ADC1_IN3/ X Port C7 Comparator negative input / Comparator 1 positive input Doc ID 15962 Rev 2 PP 27/101 Pin description Table 4. Pin number VFQFPN48 and LQFP48 STM8L151xx, STM8L152xx STM8L15x pin description (continued) Input Output Main function (after reset) High sink/source I/O level Ext. interrupt WFQFPN28 WFQFPN32 Type floating Pin name Default alternate function wpu OD 20 - PD0/TIM3_CH2/ [ADC1_TRIG](3)/ 8 LCD_SEG7(2)/ADC1_IN2 2/COMP2_INP/ COMP1_INP I/O X X X HS X Timer 3 - channel 2 / [ADC1_Trigger] / LCD segment 7 X Port D0 / ADC1_IN22 / Comparator 2 positive input / Comparator 1 positive input Port X D0(5) Timer 3 - channel 2 / [ADC1_Trigger] / ADC1_IN22 / Comparator 2 positive input / Comparator 1 positive input - 9 PD0/TIM3_CH2/ [ADC1_TRIG](3)/ I/O ADC1_IN22/COMP2_INP/ COMP1_INP PD1/TIM3_TRIG/ LCD_COM3(2)/ I/O ADC1_IN21/COMP2_INP/ COMP1_INP PD1/TIM1_CH3N/[TIM3_T RIG](3)/ LCD_COM3(2)/ I/O ADC1_IN21/COMP2_INP/ COMP1_INP PD1/TIM1_CH3/[TIM3_TR IG](3)/LCD_COM3(2)/ 9 I/O ADC1_IN21/COMP2_INP/ COMP1_INP X X X HS X 21 - X X X HS X Timer 3 - trigger / LCD_COM3 / ADC1_IN21 / comparator 2 X Port D1 positive input / Comparator 1 positive input [Timer 3 - trigger]/ TIM1 inverted channel 3 / LCD_COM3/ X Port D1 ADC1_IN21 / Comparator 2 positive input / Comparator 1 positive input Timer 1 channel 3 / [Timer 3 trigger] / LCD_COM3/ X Port D1 ADC1_IN21 / Comparator 2 positive input / Comparator 1 positive input Timer 1 - channel 1 / LCD X Port D2 segment 8 / ADC1_IN20 / Comparator 1 positive input Timer 1 - trigger / LCD segment 9 X Port D3 / ADC1_IN19 / Comparator 1 positive input Timer 1 - trigger / LCD segment 9 / ADC1_IN19 / Timer 1 break X Port D3 input / RTC calibration / Comparator 1 positive input Timer 1 - channel 2 / LCD X Port D4 segment 18 / ADC1_IN10/ Comparator 1 positive input - 10 X X X HS X - - X X X HS X PD2/TIM1_CH1 I/O 22 11 10 /LCD_SEG8(2)/ ADC1_IN20/COMP1_INP 23 12 PD3/ TIM1_TRIG/ - LCD_SEG9(2)/ADC1_IN1 9/COMP1_INP PD3/ TIM1_TRIG/ LCD_SEG9(2)/ 11 ADC1_IN19/TIM1_BKIN/ COMP1_INP/ RTC_CALIB I/O X X X HS X X X X HS X - - I/O X X X HS X PD4/TIM1_CH2 I/O 33 21 20 /LCD_SEG18(2)/ ADC1_IN10/COMP1_INP X X X HS X 28/101 Doc ID 15962 Rev 2 PP STM8L151xx, STM8L152xx Table 4. Pin number VFQFPN48 and LQFP48 Pin description STM8L15x pin description (continued) Input Output Main function (after reset) High sink/source I/O level Ext. interrupt WFQFPN28 WFQFPN32 Type floating Pin name Default alternate function wpu OD 34 22 PD5/TIM1_CH3 - /LCD_SEG19(2)/ ADC1_IN9/COMP1_INP PD6/TIM1_BKIN /LCD_SEG20(2)/ - ADC1_IN8/RTC_CALIB/ VREF_OUT/ COMP1_INP I/O X X X HS X Timer 1 - channel 3 / LCD X Port D5 segment 19 / ADC1_IN9/ Comparator 1 positive input Timer 1 - break input / LCD segment 20 / ADC1_IN8 / RTC X Port D6 calibration / Voltage reference output / Comparator 1 positive input Timer 1 - inverted channel 1/ LCD segment 21 / ADC1_IN7 / X Port D7 RTC alarm / Voltage reference output /Comparator 1 positive input X Port E0 X Port E1 X Port E2 X Port E3 X Port E4 X Port E5 LCD segment 1 Timer 1 - inverted channel 2 / LCD segment 2 Timer 1 - inverted channel 3 / LCD segment 3 LCD segment 4 LCD segment 5 LCD segment 6 / ADC1_IN23 / Comparator 2 positive input / Comparator 1 positive input LCD segment 26/PVD_IN LCD segment 27 ADC1_IN24 / DAC_OUT 35 23 I/O X X X HS X 36 24 PD7/TIM1_CH1N /LCD_SEG21(2)/ - ADC1_IN7/RTC_ALARM/ I/O VREF_OUT/ COMP1_INP - PE0/LCD_SEG1(2) PE1/TIM1_CH2N /LCD_SEG2(2) PE2/TIM1_CH3N /LCD_SEG3(2) I/O FT I/O I/O I/O I/O X X X HS X 14 15 16 17 18 19 - X X X X X X X X X X X X X X X X X X HS X HS X HS X HS X HS X HS X - PE3/LCD_SEG4(2) - PE4/LCD_SEG5 (2) PE5/LCD_SEG6(2)/ - ADC1_IN23/COMP2_INP/ I/O COMP1_INP PE6/LCD_SEG26(2)/ PVD_IN I/O I/O I/O S 47 48 32 13 13 10 11 12 9 - X X X X X X X X X HS X HS X HS X X Port E6 X Port E7 X Port F0 - PE7/LCD_SEG27(2) PF0/ADC1_IN24/ DAC_OUT - VLCD(2) - Reserved(5) - VDD - VDDA - VREF+ PP LCD booster external capacitor Reserved. Must be tied to VDD S S S Digital power supply Analog supply voltage ADC1 and DAC positive voltage reference Doc ID 15962 Rev 2 29/101 Pin description Table 4. Pin number VFQFPN48 and LQFP48 STM8L151xx, STM8L152xx STM8L15x pin description (continued) Input Output Main function (after reset) High sink/source I/O level Ext. interrupt WFQFPN28 WFQFPN32 Type floating Pin name Default alternate function wpu OD PP 9 39 40 8 7 - 7 VDD/VDDA/VREF+ 6 VSS/VSSA/VREF- VDDIO - VSSIO S S S S HS (6) Digital power supply / Analog supply voltage / ADC1 positive voltage reference I/O ground / Analog ground voltage / ADC1 negative voltage reference IOs supply voltage IOs ground voltage [USART1 synchronous clock](3) / SWIM input and output / Beep output / Infrared Timer output 1 PA0/[USART1_CK](3)/ 32 28 SWIM/BEEP/IR_TIM (6) I/O X X X X X Port A0 1. When the PA1/NRST pin is used as general purpose (PA1), it can be configured only as output push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x reference manual (RM0031). 2. Available on STM8L152xx devices only. 3. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). 5. Available on STM8L151xx devices only. 6. High Sink LED driver capability available on PA0. 4.1 System configuration options As shown in Table 4: STM8L15x pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the " Routing interface (RI) and system configuration controller" section in the STM8L15xxx reference manual (RM0031). 30/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Memory and register map 5 5.1 Memory and register map Memory mapping The memory map is shown in Figure 8. Figure 8. 0x00 0000 Memory map RAM (2 Kbytes) (1) including Stack (513 bytes) (1) Reserved 0x00 07FF 0x00 0800 0x00 0FFF 0x00 1000 0x00 5000 GPIO Ports Flash DMA1 SYSCFG ITC-EXTI RST CLK WWDG IWDG BEEP RTC SPI1 I2C1 USART1 TIM2 TIM3 TIM1 TIM4 IRTIM ADC1 DAC LCD RI COMP Data EEPROM (1 Kbyte) 0x00 13FF 0x00 1400 Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 48FF 0x00 4900 0x00 49FF 0x00 5000 0x00 57FF 0x00 5800 0x00 59FF 0x00 6000 0x00 67FF 0x00 7000 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 GPIO and peripheral registers Reserved 0x00 5050 0x00 5070 0x00 509E 0x00 50A0 0x00 50B0 0x00 50C0 0x00 50D3 0x00 50E0 0x00 50F3 0x00 5140 0x00 5200 0x00 5210 0x00 5230 0x00 5250 0x00 5280 0x00 52B0 Reserved Boot ROM (2 Kbytes) Reserved CPU/SWIM/Debug/ITC Registers Reset and interrupt vectors 0x00 52E0 0x00 52FF 0x00 5340 0x00 5380 0x00 5400 0x00 5430 0x00 5440 Medium-density Flash program memory (up to 32 Kbytes) 0x00 FFFF 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. Doc ID 15962 Rev 2 31/101 Memory and register map Table 5. Flash and RAM boundary addresses Memory area RAM Flash program memory 32 Kbytes 0x00 8000 Size 2 Kbytes 16 Kbytes Start Address 0x00 0000 0x00 8000 STM8L151xx, STM8L152xx End address 0x00 07FF 0x00 BFFF 0x00 FFFF 5.2 Table 6. Register map I/O port hardware register map Block Register label PA_ODR PA_IDR Port A PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR Port B PB_DDR PB_CR1 PB_CR2 PC_ODR PB_IDR Port C PC_DDR PC_CR1 PC_CR2 PD_ODR PD_IDR Port D PD_DDR PD_CR1 PD_CR2 PE_ODR PE_IDR Port E PE_DDR PE_CR1 PE_CR2 Register name Port A data output latch register Port A input pin value register Port A data direction register Port A control register 1 Port A control register 2 Port B data output latch register Port B input pin value register Port B data direction register Port B control register 1 Port B control register 2 Port C data output latch register Port C input pin value register Port C data direction register Port C control register 1 Port C control register 2 Port D data output latch register Port D input pin value register Port D data direction register Port D control register 1 Port D control register 2 Port E data output latch register Port E input pin value register Port E data direction register Port E control register 1 Port E control register 2 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Address 0x00 5000 0x00 5001 0x00 5002 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 5007 0x00 5008 0x00 5009 0x00 500A 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F 0x00 5010 0x00 5011 0x00 5012 0x00 5013 0x00 5014 0x00 5015 0x00 5016 0x00 5017 0x00 5018 32/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 6. I/O port hardware register map (continued) Block Register label PF_ODR PF_IDR Port F PF_DDR PF_CR1 PF_CR2 Memory and register map Address 0x00 5019 0x00 501A 0x00 501B 0x00 501C 0x00 501D Register name Port F data output latch register Port F input pin value register Port F data direction register Port F control register 1 Port F control register 2 Reset status 0x00 0x00 0x00 0x00 0x00 Table 7. General hardware register map Block Register label Register name Reset status Address 0x00 501E to 0x00 5049 0x00 5050 0x00 5051 0x00 5052 0x00 5053 0x00 5054 0x00 5065 to 0x00 506F Reserved area (44 bytes) FLASH_CR1 FLASH_CR2 Flash FLASH _PUKR FLASH _DUKR FLASH _IAPSR Flash control register 1 Flash control register 2 Flash program memory unprotection key register Data EEPROM unprotection key register Flash in-application programming status register Reserved area (11 bytes) 0x00 0x00 0x00 0x00 0x00 Doc ID 15962 Rev 2 33/101 Memory and register map Table 7. General hardware register map (continued) Block Register label DMA1_GCSR DMA1_GIR1 STM8L151xx, STM8L152xx Address 0x00 5070 0x00 5071 0x00 5072 to 0x00 5074 0x00 5075 0x00 5076 0x00 5077 0x00 5078 0x00 5079 0x00 507A 0x00 507B 0x00 507C 0x00 507D to 0x00 507E 0x00 507F 0x00 5080 0x00 5081 0x00 5082 0x00 5083 Register name DMA1 global configuration & status register DMA1 global interrupt register 1 Reserved area (3 bytes) Reset status 0xFC 0x00 DMA1_C0CR DMA1_C0SPR DMA1_C0NDTR DMA1_C0PARH DMA1_C0PARL DMA1 DMA1_C0M0ARH DMA1_C0M0ARL DMA1 channel 0 configuration register DMA1 channel 0 status & priority register DMA1 number of data to transfer register (channel 0) DMA1 peripheral address high register (channel 0) DMA1 peripheral address low register (channel 0) Reserved area (1 byte) DMA1 memory 0 address high register (channel 0) DMA1 memory 0 address low register (channel 0) Reserved area (2 bytes) 0x00 0x00 0x00 0x52 0x00 0x00 0x00 DMA1_C1CR DMA1_C1SPR DMA1_C1NDTR DMA1_C1PARH DMA1_C1PARL DMA1 channel 1 configuration register DMA1 channel 1 status & priority register DMA1 number of data to transfer register (channel 1) DMA1 peripheral address high register (channel 1) DMA1 peripheral address low register (channel 1) 0x00 0x00 0x00 0x52 0x00 34/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label Memory and register map Address 0x00 5084 0x00 5085 0x00 5086 0x00 5087 0x00 5088 0x00 5089 0x00 508A 0x00 508B 0x00 508C 0x00 508D 0x00 508E 0x00 508F Register name Reserved area (1 byte) Reset status DMA1_C1M0ARH DMA1_C1M0ARL DMA1 memory 0 address high register (channel 1) DMA1 memory 0 address low register (channel 1) Reserved area (2 bytes) 0x00 0x00 DMA1_C2CR DMA1_C2SPR DMA1_C2NDTR DMA1_C2PARH DMA1_C2PARL DMA1 channel 2 configuration register DMA1 channel 2 status & priority register DMA1 number of data to transfer register (channel 2) DMA1 peripheral address high register (channel 2) DMA1 peripheral address low register (channel 2) Reserved area (1 byte) 0x00 0x00 0x00 0x52 0x00 DMA1_C2M0ARH DMA1 DMA1_C2M0ARL DMA1 memory 0 address high register (channel 2) DMA1 memory 0 address low register (channel 2) Reserved area (2 bytes) 0x00 0x00 0x00 5090 0x00 5091 0x00 5092 0x00 5093 0x00 5094 0x00 5095 0x00 5096 0x00 5097 0x00 5098 0x00 5099 0x00 509A 0x00 509B to 0x00 509D 0x00 509E SYSCFG 0x00 509F DMA1_C3CR DMA1_C3SPR DMA1_C3NDTR DMA1_C3PARH_ C3M1ARH DMA1_C3PARL_ C3M1ARL DMA1 channel 3 configuration register DMA1 channel 3 status & priority register DMA1 number of data to transfer register (channel 3) DMA1 peripheral address high register (channel 3) DMA1 peripheral address low register (channel 3) Reserved area (1 byte) 0x00 0x00 0x00 0x40 0x00 DMA1_C3M0ARH DMA1_C3M0ARL DMA1 memory 0 address high register (channel 3) DMA1 memory 0 address low register (channel 3) Reserved area (3 bytes) 0x00 0x00 SYSCFG_RMPCR1 SYSCFG_RMPCR2 Remapping register 1 Remapping register 2 0x00 0x00 Doc ID 15962 Rev 2 35/101 Memory and register map Table 7. General hardware register map (continued) Block Register label EXTI_CR1 EXTI_CR2 EXTI_CR3 ITC - EXTI 0x00 50A3 0x00 50A4 0x00 50A5 0x00 50A6 0x00 50A7 0x00 50A8 0x00 50A9 to 0x00 50AF 0x00 50B0 RST 0x00 50B1 0x00 50B2 PWR 0x00 50B3 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C6 0x00 50C7 CLK 0x00 50C8 0x00 50C9 0x00 50CA 0x00 50CB 0x00 50CC 0x00 50CD 0x00 50CE 0x00 50CF CLK_SWR CLK_SWCR CLK_CSSR CLK_CBEEPR CLK_HSICALR CLK_HSITRIMR CLK_HSIUNLCKR CLK_REGCSR CLK_DIVR CLK_CRTCR CLK_ICKR CLK_PCKENR1 CLK_PCKENR2 CLK_CCOR CLK_ECKR CLK_SCSR PWR_CSR2 RST_SR PWR_CSR1 RST_CR WFE EXTI_SR1 EXTI_SR2 EXTI_CONF WFE_CR1 WFE_CR2 WFE_CR3 STM8L151xx, STM8L152xx Address 0x00 50A0 0x00 50A1 0x00 50A2 Register name External interrupt control register 1 External interrupt control register 2 External interrupt control register 3 External interrupt status register 1 External interrupt status register 2 External interrupt port select register WFE control register 1 WFE control register 2 WFE control register 3 Reserved area (7 bytes) Reset control register Reset status register Power control and status register 1 Power control and status register 2 Reserved area (12 bytes) Clock master divider register Clock RTC register Internal clock control register Peripheral clock gating register 1 Peripheral clock gating register 2 Configurable clock control register External clock control register System clock status register System clock switch register Clock switch control register Clock security system register Clock BEEP register HSI calibration register HSI clock calibration trimming register HSI unlock register Main regulator control status register Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x00 0x11 0x00 0x00 0x00 0x00 0x01 0x01 0bxxxx0000 0x00 0x00 0x00 0x00 0x00 0bxx11100x 36/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label Memory and register map Address 0x00 50D0 to 0x00 50D2 0x00 50D3 Register name Reset status Reserved area (3 bytes) WWDG_CR WWDG WWDG_WR WWDG control register WWDR window register Reserved area (11 bytes) IWDG_KR IWDG IWDG_PR IWDG_RLR IWDG key register IWDG prescaler register IWDG reload register Reserved area (13 bytes) BEEP_CSR1 BEEP BEEP_CSR2 BEEP control/status register 1 Reserved area (2 bytes) BEEP control/status register 2 Reserved area (76 bytes) 0x1F 0x00 0x 0x00 0xFF 0x7F 0x7F 0x00 50D4 0x00 50D5 to 00 50DF 0x00 50E0 0x00 50E1 0x00 50E2 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 513F Doc ID 15962 Rev 2 37/101 Memory and register map Table 7. General hardware register map (continued) Block Register label RTC_TR1 RTC_TR2 RTC_TR3 STM8L151xx, STM8L152xx Address 0x00 5140 0x00 5141 0x00 5142 0x00 5143 0x00 5144 0x00 5145 0x00 5146 0x00 5147 0x00 5148 0x00 5149 0x00 514A 0x00 514B 0x00 514C 0x00 514D 0x00 514E 0x00 514F 0x00 5150 0x00 5151 0x00 5152 0x00 5153 0x00 5154 0x00 5155 0x00 5156 to 0x00 5158 0x00 5159 0x00 515A 0x00 515B 0x00 515C 0x00 515D 0x00 515E 0x00 515F 0x00 5160 to 0x00 51FF Register name Time register 1 Time register 2 Time register 3 Reserved area (1 byte) Reset status 0x00 0x00 0x00 RTC_DR1 RTC_DR2 RTC_DR3 Date register 1 Date register 2 Date register 3 Reserved area (1 byte) 0x00 0x00 0x00 RTC_CR1 RTC_CR2 RTC_CR3 Control register 1 Control register 2 Control register 3 Reserved area (1 byte) 0x00 0x00 0x00 RTC_ISR1 RTC_ISR2 RTC RTC_SPRERH RTC_SPRERL RTC_APRER Initialization and status register 1 Initialization and Status register 2 Reserved area (2 bytes) Synchronous prescaler register high Synchronous prescaler register low Asynchronous prescaler register Reserved area (1 byte) 0x00 0x00 - RTC_WUTRH RTC_WUTRL Wakeup timer register high Wakeup timer register low Reserved area (3 bytes) - RTC_WPR Write protection register Reserved area (2 bytes) 0x00 RTC_ALRMAR1 RTC_ALRMAR2 RTC_ALRMAR3 RTC_ALRMAR4 Alarm A register 1 Alarm A register 2 Alarm A register 3 Alarm A register 4 Reserved area (160 bytes) 0x00 0x00 0x00 0x00 38/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label SPI1_CR1 SPI1_CR2 SPI1_ICR SPI1_SR SPI1 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to 0x00 520F 0x00 5210 0x00 5211 0x00 5212 0x00 5213 0x00 5214 0x00 5215 0x00 5216 0x00 5217 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C 0x00 521D 0x00 521E 0x00 521F to 0x00 522F I2C1 I2C1_DR I2C1_SR1 I2C1_SR2 I2C1_SR3 I2C1_ITR I2C1_CCRL I2C1_CCRH I2C1_TRISER I2C1_PECR I2C1_CR1 I2C1_CR2 I2C1_FREQR I2C1_OARL I2C1_OARH SPI1_DR SPI1_CRCPR SPI1_RXCRCR SPI1_TXCRCR Memory and register map Address 0x00 5200 0x00 5201 0x00 5202 0x00 5203 Register name SPI1 control register 1 SPI1 control register 2 SPI1 interrupt control register SPI1 status register SPI1 data register SPI1 CRC polynomial register SPI1 Rx CRC register SPI1 Tx CRC register Reserved area (8 bytes) I2C1 control register 1 I2C1 control register 2 I2C1 frequency register I2C1 own address register low I2C1 own address register high Reserved (1 byte) I2C1 data register I2C1 status register 1 I2C1 status register 2 I2C1 status register 3 I2C1 interrupt control register I2C1 clock control register low I2C1 clock control register high I2C1 TRISE register I2C1 packet error checking register Reserved area (17 bytes) Reset status 0x00 0x00 0x00 0x02 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0x 0x00 0x00 0x00 0x02 0x00 Doc ID 15962 Rev 2 39/101 Memory and register map Table 7. General hardware register map (continued) Block Register label USART1_SR USART1_DR USART1_BRR1 USART1_BRR2 USART1_CR1 USART1 USART1_CR2 USART1_CR3 USART1_CR4 USART1_CR5 USART1_GTR USART1_PSCR STM8L151xx, STM8L152xx Address 0x00 5230 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 0x00 5236 0x00 5237 0x00 5238 0x00 5239 0x00 523A 0x00 523B to 0x00 524F Register name USART1 status register USART1 data register USART1 baud rate register 1 USART1 baud rate register 2 USART1 control register 1 USART1 control register 2 USART1 control register 3 USART1 control register 4 USART1 control register 5 USART1 guard time register USART1 prescaler register Reserved area (21 bytes) Reset status 0xC0 undefined 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 40/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label TIM2_CR1 TIM2_CR2 TIM2_SMCR TIM2_ETR TIM2_DER TIM2_IER TIM2_SR1 TIM2_SR2 TIM2_EGR TIM2_CCMR1 TIM2_CCMR2 TIM2 TIM2_CCER1 TIM2_CNTRH TIM2_CNTRL TIM2_PSCR TIM2_ARRH TIM2_ARRL TIM2_CCR1H TIM2_CCR1L TIM2_CCR2H TIM2_CCR2L TIM2_BKR TIM2_OISR Memory and register map Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 0x00 5267 to 0x00 527F Register name TIM2 control register 1 TIM2 control register 2 TIM2 Slave mode control register TIM2 external trigger register TIM2 DMA1 request enable register TIM2 interrupt enable register TIM2 status register 1 TIM2 status register 2 TIM2 event generation register TIM2 capture/compare mode register 1 TIM2 capture/compare mode register 2 TIM2 capture/compare enable register 1 TIM2 counter high TIM2 counter low TIM2 prescaler register TIM2 auto-reload register high TIM2 auto-reload register low TIM2 capture/compare register 1 high TIM2 capture/compare register 1 low TIM2 capture/compare register 2 high TIM2 capture/compare register 2 low TIM2 break register TIM2 output idle state register Reserved area (25 bytes) Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15962 Rev 2 41/101 Memory and register map Table 7. General hardware register map (continued) Block Register label TIM3_CR1 TIM3_CR2 TIM3_SMCR TIM3_ETR TIM3_DER TIM3_IER TIM3_SR1 TIM3_SR2 TIM3_EGR TIM3_CCMR1 TIM3_CCMR2 TIM3 TIM3_CCER1 TIM3_CNTRH TIM3_CNTRL TIM3_PSCR TIM3_ARRH TIM3_ARRL TIM3_CCR1H TIM3_CCR1L TIM3_CCR2H TIM3_CCR2L TIM3_BKR TIM3_OISR STM8L151xx, STM8L152xx Address 0x00 5280 0x00 5281 0x00 5282 0x00 5283 0x00 5284 0x00 5285 0x00 5286 0x00 5287 0x00 5288 0x00 5289 0x00 528A 0x00 528B 0x00 528C 0x00 528D 0x00 528E 0x00 528F 0x00 5290 0x00 5291 0x00 5292 0x00 5293 0x00 5294 0x00 5295 0x00 5296 0x00 5297 to 0x00 52AF Register name TIM3 control register 1 TIM3 control register 2 TIM3 Slave mode control register TIM3 external trigger register TIM3 DMA1 request enable register TIM3 interrupt enable register TIM3 status register 1 TIM3 status register 2 TIM3 event generation register TIM3 Capture/Compare mode register 1 TIM3 Capture/Compare mode register 2 TIM3 Capture/Compare enable register 1 TIM3 counter high TIM3 counter low TIM3 prescaler register TIM3 Auto-reload register high TIM3 Auto-reload register low TIM3 Capture/Compare register 1 high TIM3 Capture/Compare register 1 low TIM3 Capture/Compare register 2 high TIM3 Capture/Compare register 2 low TIM3 break register TIM3 output idle state register Reserved area (25 bytes) Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 42/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label TIM1_CR1 TIM1_CR2 TIM1_SMCR TIM1_ETR TIM1_DER TIM1_IER TIM1_SR1 TIM1_SR2 TIM1_EGR TIM1_CCMR1 TIM1_CCMR2 TIM1_CCMR3 TIM1_CCMR4 TIM1_CCER1 TIM1_CCER2 TIM1_CNTRH TIM1_CNTRL TIM1 0x00 52C1 0x00 52C2 0x00 52C3 0x00 52C4 0x00 52C5 0x00 52C6 0x00 52C7 0x00 52C8 0x00 52C9 0x00 52CA 0x00 52CB 0x00 52CC 0x00 52CD 0x00 52CE 0x00 52CF 0x00 52D0 0x00 52D1 TIM1_PSCRH TIM1_PSCRL TIM1_ARRH TIM1_ARRL TIM1_RCR TIM1_CCR1H TIM1_CCR1L TIM1_CCR2H TIM1_CCR2L TIM1_CCR3H TIM1_CCR3L TIM1_CCR4H TIM1_CCR4L TIM1_BKR TIM1_DTR TIM1_OISR TIM1_DCR1 Memory and register map Address 0x00 52B0 0x00 52B1 0x00 52B2 0x00 52B3 0x00 52B4 0x00 52B5 0x00 52B6 0x00 52B7 0x00 52B8 0x00 52B9 0x00 52BA 0x00 52BB 0x00 52BC 0x00 52BD 0x00 52BE 0x00 52BF 0x00 52C0 Register name TIM1 control register 1 TIM1 control register 2 TIM1 Slave mode control register TIM1 external trigger register TIM1 DMA1 request enable register TIM1 Interrupt enable register TIM1 status register 1 TIM1 status register 2 TIM1 event generation register TIM1 Capture/Compare mode register 1 TIM1 Capture/Compare mode register 2 TIM1 Capture/Compare mode register 3 TIM1 Capture/Compare mode register 4 TIM1 Capture/Compare enable register 1 TIM1 Capture/Compare enable register 2 TIM1 counter high TIM1 counter low TIM1 prescaler register high TIM1 prescaler register low TIM1 Auto-reload register high TIM1 Auto-reload register low TIM1 Repetition counter register TIM1 Capture/Compare register 1 high TIM1 Capture/Compare register 1 low TIM1 Capture/Compare register 2 high TIM1 Capture/Compare register 2 low TIM1 Capture/Compare register 3 high TIM1 Capture/Compare register 3 low TIM1 Capture/Compare register 4 high TIM1 Capture/Compare register 4 low TIM1 break register TIM1 dead-time register TIM1 output idle state register DMA1 control register 1 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15962 Rev 2 43/101 Memory and register map Table 7. General hardware register map (continued) Block Register label TIM1_DCR2 TIM1_DMA1R STM8L151xx, STM8L152xx Address 0x00 52D2 0x00 52D3 0x00 52D4 to 0x00 52DF 0x00 52E0 0x00 52E1 0x00 52E2 0x00 52E3 0x00 52E4 Register name TIM1 DMA1 control register 2 TIM1 DMA1 address for burst mode Reserved area (12 bytes) Reset status 0x00 0x00 TIM4_CR1 TIM4_CR2 TIM4_SMCR TIM4_DER TIM4_IER TIM4 TIM4_SR1 TIM4_EGR TIM4_CNTR TIM4_PSCR TIM4_ARR TIM4 control register 1 TIM4 control register 2 TIM4 Slave mode control register TIM4 DMA1 request enable register TIM4 Interrupt enable register TIM4 status register 1 TIM4 Event generation register TIM4 counter TIM4 prescaler register TIM4 Auto-reload register Reserved area (21 bytes) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 52E5 0x00 52E6 0x00 52E7 0x00 52E8 0x00 52E9 0x00 52EA to 0x00 52FE 0x00 52FF 0x00 5300 to 0x00 533F 0x00 5340 0x00 5341 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 ADC1 0x00 5347 0x00 5348 0x00 5349 0x00 534A 0x00 534B 0x00 534C 0x00 534D IRTIM IR_CR Infrared control register Reserved area (64 bytes) 0x00 ADC1_CR1 ADC1_CR2 ADC1_CR3 ADC1_SR ADC1_DRH ADC1_DRL ADC1_HTRH ADC1_HTRL ADC1_LTRH ADC1_LTRL ADC1_SQR1 ADC1_SQR2 ADC1_SQR3 ADC1_SQR4 ADC1 configuration register 1 ADC1 configuration register 2 ADC1 configuration register 3 ADC1 status register ADC1 data register high ADC1 data register low ADC1 high threshold register high ADC1 high threshold register low ADC1 low threshold register high ADC1 low threshold register low ADC1 channel sequence 1 register ADC1 channel sequence 2 register ADC1 channel sequence 3 register ADC1 channel sequence 4 register 0x00 0x00 0x1F 0x00 0x00 0x00 0x0F 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 44/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label ADC1_TRIGR1 ADC1_TRIGR2 ADC1 0x00 5350 0x00 5351 0x00 5352 to 0x00 537F 0x00 5380 0x00 5381 0x00 5382 to 0x00 5383 0x00 5384 0x00 5385 0x00 5386 to 0x00 5387 0x00 5388 0x00 5389 DAC 0x00 538A to 0x00 538B 0x00 538C 0x00 538D 0x00 538E to 0x00 538F 0x00 5390 0x00 5391 to 0x00 53AB 0x00 53AC 0x00 53AD 0x00 53AE to 0x00 53FF DAC_DORH DAC_DORL DAC_DHR8 DAC_LDHRH DAC_LDHRL DAC_RDHRH DAC_RDHRL DAC_SWTRIGR DAC_SR DAC_CR1 DAC_CR2 Memory and register map Address 0x00 534E 0x00 534F Register name ADC1 trigger disable 1 ADC1 trigger disable 2 ADC1 trigger disable 3 ADC1 trigger disable 4 Reserved area (46 bytes) DAC control register 1 DAC control register 2 Reserved area (2 bytes) DAC software trigger register DAC status register Reserved area (2 bytes) DAC right aligned data holding register high DAC right aligned data holding register low Reserved area (2 bytes) DAC left aligned data holding register high DAC left aligned data holding register low Reserved area (2 bytes) DAC 8-bit data holding register Reserved area (27 bytes) DAC data output register high DAC data output register low Reserved area (82 bytes) Reset status 0x00 0x00 0x00 0x00 ADC1_TRIGR3 ADC1_TRIGR4 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15962 Rev 2 45/101 Memory and register map Table 7. General hardware register map (continued) Block Register label LCD_CR1 LCD_CR2 LCD_CR3 LCD_FRQ LCD 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 to 0x00 540B 0x00 540C 0x00 540D 0x00 540E 0x00 540F 0x00 5410 0x00 5411 0x00 5412 0x00 5413 0x00 5414 0x00 5415 0x00 5416 0x00 5417 0x00 5418 0x00 5419 0x00 541A to 0x00 542F LCD LCD_RAM0 LCD_RAM1 LCD_RAM2 LCD_RAM3 LCD_RAM4 LCD_RAM5 LCD_RAM6 LCD_RAM7 LCD_RAM8 LCD_RAM9 LCD_RAM10 LCD_RAM11 LCD_RAM12 LCD_RAM13 LCD_PM0 LCD_PM1 LCD_PM2 LCD_PM3 STM8L151xx, STM8L152xx Address 0x00 5400 0x00 5401 0x00 5402 0x00 5403 Register name LCD control register 1 LCD control register 2 LCD control register 3 LCD frequency selection register LCD Port mask register 0 LCD Port mask register 1 LCD Port mask register 2 LCD Port mask register 3 Reserved area (4 bytes) LCD display memory 0 LCD display memory 1 LCD display memory 2 LCD display memory 3 LCD display memory 4 LCD display memory 5 LCD display memory 6 LCD display memory 7 LCD display memory 8 LCD display memory 9 LCD display memory 10 LCD display memory 11 LCD display memory 12 LCD display memory 13 Reserved area (22 bytes) Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 46/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 7. General hardware register map (continued) Block Register label Memory and register map Address 0x00 5430 0x00 5431 0x00 5432 0x00 5433 0x00 5434 0x00 5435 0x00 5436 0x00 5437 Register name Reserved area (1 byte) Reset status 0x00 0x00 0x00 undefined undefined undefined 0x00 0x00 0x00 0x00 0x00 0x00 0x3F 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RI_ICR1 RI_ICR2 RI_IOIR1 RI_IOIR2 RI_IOIR3 RI_IOCMR1 RI_IOCMR3 RI RI_IOCMR3 RI_IOSR1 RI_IOSR2 RI_IOSR3 Timer input capture routing register 1 Timer input capture routing register 2 I/O input register 1 I/O input register 2 I/O input register 3 I/O control mode register 1 I/O control mode register 2 I/O control mode register 3 I/O switch register 1 I/O switch register 2 I/O switch register 3 Reserved area (1 byte) 0x00 5438 0x00 5439 0x00 543A 0x00 543B 0x00 543C 0x00 543D 0x00 543E 0x00 543F 0x00 5440 0x00 5441 0x00 5442 0x00 5443 0x00 5444 COMP RI_ASCR1 RI_ASCR2 RI_RCR COMP_CSR1 COMP_CSR2 COMP_CSR3 COMP_CSR4 COMP_CSR5 Analog switch register 1 Analog switch register 2 Resistor control register 1 Comparator control and status register 1 Comparator control and status register 2 Comparator control and status register 3 Comparator control and status register 4 Comparator control and status register 5 Doc ID 15962 Rev 2 47/101 Memory and register map Table 8. Address 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 0x00 7F05 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 7F5F 0x00 7F60 0x00 7F70 0x00 7F71 0x00 7F72 0x00 7F73 ITC-SPR 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F SWIM SWIM_CSR ITC_SPR5 ITC_SPR6 ITC_SPR7 ITC_SPR8 CPU(1) STM8L151xx, STM8L152xx CPU/SWIM/debug module/interrupt controller registers Block Register Label A PCE PCH PCL XH XL YH YL SPH SPL CCR Register Name Accumulator Program counter extended Program counter high Program counter low X index register high X index register low Y index register high Y index register low Stack pointer high Stack pointer low Condition code register Reserved area (85 bytes) CPU CFG_GCR ITC_SPR1 ITC_SPR2 ITC_SPR3 ITC_SPR4 Global configuration register Interrupt Software priority register 1 Interrupt Software priority register 2 Interrupt Software priority register 3 Interrupt Software priority register 4 Interrupt Software priority register 5 Interrupt Software priority register 6 Interrupt Software priority register 7 Interrupt Software priority register 8 Reserved area (2 bytes) SWIM control status register Reserved area (15 bytes) 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Reset Status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0xFF 0x28 48/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 8. Address 0x00 7F90 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A 0x00 7F9B to 0x00 7F9F 1. Accessible by debug module only Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Block Register Label DM_BK1RE DM_BK1RH DM_BK1RL DM_BK2RE DM_BK2RH DM DM_BK2RL DM_CR1 DM_CR2 DM_CSR1 DM_CSR2 DM_ENFCTR Register Name DM breakpoint 1 register extended byte DM breakpoint 1 register high byte DM breakpoint 1 register low byte DM breakpoint 2 register extended byte DM breakpoint 2 register high byte DM breakpoint 2 register low byte DM Debug module control register 1 DM Debug module control register 2 DM Debug module control/status register 1 DM Debug module control/status register 2 DM enable function register Reserved area (5 bytes) Reset Status 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x10 0x00 0xFF Doc ID 15962 Rev 2 49/101 Interrupt vector mapping STM8L151xx, STM8L152xx 6 Table 9. IRQ No. Interrupt vector mapping Interrupt mapping Wakeup from Halt mode Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Wakeup from Active-halt mode Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Wakeup from Wait (WFI mode) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Wakeup from Wait (WFE mode)(1) Yes Yes(2) Yes (2) Source block RESET TRAP Reset Description Vector address 0x00 8000 0x00 8004 0x00 800C 0x00 8010 0x00 8014 0x00 8018 0x00 801C 0x00 8020 0x00 8024 0x00 8028 0x00 802C 0x00 8030 0x00 8034 0x00 8038 0x00 803C 0x00 8040 0x00 8044 0x00 8048 0x00 804C Software interrupt EOP/WR_PG_DIS DMA1 channels 0/1 DMA1 channels 2/3 RTC alarm interrupt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FLASH DMA1 0/1 DMA1 2/3 RTC Yes(2) Yes Yes(2) Yes(2) Yes(2) Yes Yes (2) (2) EXTI PortE/F interrupt/PVD E/F/PVD(3) interrupt EXTIB EXTID EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 EXTI5 EXTI6 EXTI7 LCD CLK/ TIM1/ DAC COMP /ADC1 TIM2 TIM2 TIM3 TIM3 TIM1 TIM1 External interrupt port B External interrupt port D External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 LCD interrupt System clock switch/CSS interrupt/TIM1 Break/DAC Comparator interrupt/ADC1 Update /Overflow/Trigger/Break Capture/Compare Update /Overflow/Trigger/Break Capture/Compare Update /Overflow/Trigger/ COM Capture/Compare Yes(2) Yes Yes (2) (2) Yes(2) Yes(2) Yes (2) Yes Yes 18 19 20 21 22 23 24 Yes - Yes - Yes Yes Yes Yes Yes - Yes(2) Yes(2) Yes(2) Yes(2) Yes(2) Yes(2) Yes(2) 0x00 8050 0x00 8054 0x00 8058 0x00 805C 0x00 8060 0x00 8064 0x00 8068 50/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 9. IRQ No. 25 26 27 Interrupt vector mapping Interrupt mapping (continued) Wakeup from Halt mode Yes Wakeup from Active-halt mode Yes Wakeup from Wait (WFI mode) Yes Yes Yes Wakeup from Wait (WFE mode)(1) Yes(2) Yes(2) Yes(2) Vector address 0x00 806C 0x00 8070 0x00 8074 Source block TIM4 SPI1 USART 1 Description Update/overflow/trigger End of Transfer Transmission complete/transmit data register empty Receive Register Data full/overrun/idle line detected/parity error I2C1 interrupt(4) 28 29 USART 1 I2C1 Yes Yes Yes Yes Yes(2) Yes(2) 0x00 8078 0x00 807C 1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. 2. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing. 3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031). 4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. Doc ID 15962 Rev 2 51/101 Option bytes STM8L151xx, STM8L152xx 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. The option bytes can also be modified `on the fly' by the application in IAP mode, except for the ROP, UBC and PCODESIZE values which can only be taken into account when they are modified in ICP mode (with the SWIM). Refer to the STM8L15x Flash programming manual (PM0051) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 10. Addr. Option byte addresses Option name Read-out protection (ROP) UBC(User Boot code size) PCODESIZE Independent watchdog option Option byte No. OPT1 Option bits 7 6 5 4 3 ROP[7:0] 2 1 0 Factory default setting 0x00 00 4800 00 4802 00 4807 00 4808 OPT3 OPT8 OPT5 [3:0] Reserved UBC[7:0] PCODE[7:0] WWDG WWDG IWDG _HALT _HW _HALT IWDG _HW 0x00 0x00 0x00 00 4809 Number of stabilization clock cycles for OPT10 HSE and LSE oscillators Brownout reset OPT11 [3:0] (BOR) Reserved HSECNT[1:0] LSECNT[1:0] 0x00 00 480A Reserved BOR_TH BOR_ ON 0x01 52/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Option bytes Table 11. Option byte No. Option byte description Option description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable Readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L15x reference manual (RM0031). UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01: the UBC contains only the interrupt vectors. 0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt vectors. 0x03 - Page 0 to 3 reserved for UBC, memory write-protected 0xFF - Page 0 to 255 reserved for UBC, memory write-protected Refer to User boot code section in the STM8L15x reference manual (RM0031). PCODESIZE[7:0] Size of the proprietary code area 0x00: no proprietary code area 0x02: Page 0 and 1 reserved for the proprietary code and read/write protected. Page 0 contains only the interrupt vectors. 0xFF - Page 0 o 254 reserved for the proprietary code. Only page 1 to 254 are read/write protected. Page 255 is always left free. Refer to Proprietary code area (PCODE) section in the STM8L reference manual (RM0013) for more details. IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode OPT1 OPT2 OPT3 WWDG_HW: Window watchdog 0: Window watchdog activated by software 1: Window watchdog activated by hardware WWDG_HALT: Window window watchdog reset on Halt/Active-halt 0: Window watchdog stopped in Halt mode 1: Window watchdog generates a reset when MCU enters Halt mode HSECNT: Number of HSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles OPT4 LSECNT: Number of LSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles Doc ID 15962 Rev 2 53/101 Option bytes Table 11. Option byte No. BOR_ON: 0 - Brownout reset off 1 - Brownout reset on STM8L151xx, STM8L152xx Option byte description (continued) Option description OPT5 BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 16 for details on the thresholds according to the value of BOR_TH bits. 54/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8 8.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 8.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 C and TA = TA max (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 8.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 8.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 8.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Figure 9. Pin loading conditions STM8L PIN 50 pF Doc ID 15962 Rev 2 55/101 Electrical parameters STM8L151xx, STM8L152xx 8.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10. Pin input voltage STM8L PIN VIN 8.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 12. Voltage characteristics Ratings External supply voltage (including VDDA and VDDIO)(1) Input voltage on true open-drain pins (PC0 and PC1) VIN Input voltage on FT pins (PA7 and PE0) Input voltage on any other pin (2) VESD Electrostatic discharge voltage Min -0.3 VSS-0.3 VSS-0.3 VSS-0.3 Max 4.0 VDD + 4.6 VDD + 4.6 4.6 Unit Symbol VDD- VSS V see Absolute maximum ratings (electrical sensitivity) on page 90 1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN max imum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 13. Symbol IVDD IVSS Electrical parameters Current characteristics Ratings Total current into VDD power line (source) Total current out of VSS ground line (sink) Output current sunk by IR_TIM pin (with high sink LED driver capability) Max. 80 80 80 25 - 25 5 25 mA Unit IIO Output current sunk by any other I/O and control pin Output current source by any I/Os and control pin IINJ(PIN) (1) Injected current on any pin (2) IINJ(PIN) (1) Total injected current (sum of all I/O and control pins) (2) 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Maximum junction temperature Min -65 to +150 C 150 Unit Doc ID 15962 Rev 2 57/101 Electrical parameters STM8L151xx, STM8L152xx 8.3 Operating conditions Subject to general operating conditions for VDD and TA. 8.3.1 Table 15. Symbol fSYSCLK(1) VDD VDDA General operating conditions General operating conditions Parameter System clock frequency Standard operating voltage Analog operating voltage ADC not used ADC used Must be at the same potential as VDD Conditions 1.65 V VDD < 3.6 V Min 0 1.65(2) 1.65(2) 1.8 Max 16 3.6 3.6 3.6 TBD TBD (5) Unit MHz V V V VFQFPN48 (4) Power dissipation at TA= 85 C for suffix 6 devices PD(3) Power dissipation at TA= 125 C for suffix 3 devices LQFP48 WFQFPN32 LQFP32 WFQFPN28 (6) VFQFPN48(4) LQFP48 WFQFPN32(5) LQFP32 WFQFPN28(6) 1.65 V VDD < 3.6 V (6 suffix version) TA Temperature range 1.65 V VDD < 3.6 V (3 suffix version) -40 C TA < 85 C (6 suffix version) -40 C TA < 125 C (3 suffix version) -40 -40 -40 -40 TBD TBD TBD mW TBD TBD TBD TBD TBD 85 C 125 105 C 130 TJ Junction temperature range 1. fSYSCLK = fCPU 2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled. 3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ with TJmax in this table and in "Thermal characteristics" JA JA table. 4. VFQFPN48 package is used in the sampling phase. In the production phase, the UFQFPN48 package will be used (with a thickness equal to 0.6 mm). 5. WFQFPN32 package is used in the sampling phase. In the production phase, the UFQFPN32 package will be used (with a thickness equal to 0.6 mm). 6. WFQFPN28 package is used in the sampling phase. In the production phase, the UFQFPN28 package will be used (with a thickness equal to 0.6 mm). 58/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8.3.2 Table 16. Symbol tVDD Power-up / power-down operating conditions Operating conditions at power-up / power-down (1) Parameter VDD rise time rate VDD fall time rate Conditions Min 0(2) 0(2) VDD rising Falling edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1.5 1.7 1.76 1.93 2.03 2.30 2.41 2.55 2.66 2.80 2.90 1.85 1.94 2.04 2.14 2.24 2.34 2.44 2.54 2.64 2.74 2.83 2.94 3.05 3.15 Typ Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD V s/V ms Unit tTEMP VPDR VBOR0 Reset release delay Power-down reset threshold Brown-out reset threshold 0 (BOR_TH[2:0]=000) Brown-out reset threshold 1 (BOR_TH[2:0]=001) Brown-out reset threshold 2 (BOR_TH[2:0]=010) Brown-out reset threshold 3 (BOR_TH[2:0]=011) Brown-out reset threshold 4 (BOR_TH[2:0]=100) PVD threshold 0 VBOR1 VBOR2 VBOR3 VBOR4 VPVD0 Rising edge Falling edge PVD threshold 1 Rising edge Falling edge PVD threshold 2 Rising edge Falling edge PVD threshold 3 Rising edge Falling edge PVD threshold 4 Rising edge Falling edge PVD threshold 5 Rising edge Falling edge PVD threshold 6 Rising edge VPVD1 VPVD2 VPVD3 VPVD4 VPVD5 VPVD6 1. Based on characterization results, unless otherwise specified. 2. Guaranteed by design, not tested in production. Doc ID 15962 Rev 2 59/101 Electrical parameters Figure 11. POR/BOR thresholds STM8L151xx, STM8L152xx Vdd Operating power supply Vdd Internal NRST 60/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8.3.3 Supply current characteristics Total current consumption The MCU is placed under the following conditions: All I/O pins in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD and TA. Table 17. Symbol Total current consumption in Run mode(1) Max Parameter Conditions(2) Typ 55C fCPU = 125 kHz 0.5 fCPU = 1 MHz HSI RC osc. fCPU = 4 MHz (16 MHz) fCPU = 8 MHz fCPU = 16 MHz 0.6 0.9 1.3 2 TBD TBD TBD TBD TBD 85 C 105 C 125 C (3) (4) (4) Unit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD (6) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD (6) All peripherals OFF, Supply code executed IDD(RUN) current in HSE from RAM, run mode(5) V from 1.65 V external DD clock to 3.6 V (16 MHz) fCPU = 125 kHz TBD TBD fCPU = 1 MHz fCPU = 4 MHz fCPU = 8 MHz TBD TBD TBD TBD TBD TBD mA fCPU = 16 MHz TBD TBD LSI RC osc. f = LSI (typ. 38 kHz) CPU LSE external clock fCPU = LSE (32.768 kHz) TBD TBD TBD TBD (6) TBD TBD (6) Doc ID 15962 Rev 2 61/101 Electrical parameters Table 17. Symbol STM8L151xx, STM8L152xx Total current consumption in Run mode(1) (continued) Max Parameter Conditions(2) Typ 55C fCPU = 125 kHz TBD TBD fCPU = 1 MHz HSI RC osc. fCPU = 4 MHz fCPU = 8 MHz All peripherals OFF, code executed from HSE Flash, VDD from 1.65 V external clock to 3.6 V (16 MHz) 0.7 1.4 2.3 TBD TBD TBD 85 C 105 C 125 C (3) (4) (4) Unit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA fCPU = 16 MHz TBD TBD Supply IDD(RUN) current in run mode fCPU = 125 kHz TBD TBD fCPU = 1 MHz fCPU = 4 MHz fCPU = 8 MHz TBD TBD TBD TBD TBD TBD fCPU = 16 MHz TBD TBD LSI RC osc. fCPU = LSI TBD TBD TBD LSE external fCPU = LSE clock (32.768 kHz) 1. Based on characterization results, unless otherwise specified TBD TBD TBD 2. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fSYSCLK 3. For devices with suffix 6. 4. For devices with suffix 3. 5. CPU executing typical data processing 6. Data guaranteed, each individual device tested in production. 62/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 18. Total current consumption in Wait mode(1) Electrical parameters Max Symbol Parameter Conditions(2) Typ 55C fCPU = 125 kHz 430 fCPU = 1 MHz HSI CPU not clocked, all peripherals OFF, code executed from RAM with Flash switched OFF, VDD from 1.65 V to 3.6 V fCPU = 4 MHz fCPU = 8 MHz fCPU = 16 MHz 450 515 600 770 TBD TBD TBD TBD TBD 85 C 105 C 125 C (3) (4) (4) Unit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A Supply IDD(Wait) current in Wait mode fCPU = 125 kHz TBD TBD HSE crystal oscillator (16 MHz) fCPU = 1 MHz fCPU = 4 MHz fCPU = 8 MHz TBD TBD TBD TBD TBD TBD fCPU = 16 MHz TBD TBD LSI fCPU = LSI 32 TBD TBD TBD TBD TBD TBD TBD LSE crystal fCPU = LSE oscillator (32.768 kHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A fCPU = 125 kHz 480 fCPU = 1 MHz HSI fCPU = 4 MHz fCPU = 8 MHz CPU not clocked, all peripherals OFF, code executed from Flash, VDD from 1.65 V to 3.6 V fCPU = 16 MHz 500 560 660 840 Supply IDD(Wait) current in Wait mode fCPU = 125 kHz TBD TBD HSE crystal oscillator (16 MHz) fCPU = 1 MHz fCPU = 4 MHz fCPU = 8 MHz TBD TBD TBD TBD TBD TBD fCPU = 16 MHz TBD TBD LSI fCPU = LSI 83 TBD TBD LSE crystal fCPU = LSE oscillator (32.768 kHz) 1. Based on characterization results, unless specified TBD TBD TBD 2. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU = fSYSCLK 3. For temperature range 6. 4. For temperature range 3. Doc ID 15962 Rev 2 63/101 Electrical parameters STM8L151xx, STM8L152xx Table 19. Symbol Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V (1)(2) Parameter Conditions TA = -40 C to 25 C TA = 55 C all peripherals OFF TA = 85 C TA = 105 C LSI RC osc. (at 38 kHz) TA = 125 C TA = -40 C to 25 C with TIM2 active(3) TA = 55 C TA = 85 C TA = 105 C Typ 5.4 TBD 6.8 9.2 13.4 5.7 TBD 7.2 9.4 13.8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A Max Unit IDD(LPR) Supply current in Low power run mode TA = 125 C TA = -40 C to 25 C TA = 55 C all peripherals OFF TA = 85 C TA = 105 C LSE external clock (32.768 kHz) TA = 125 C TA = -40 C to 25 C with TIM2 active (3) TA = 55 C TA = 85 C TA = 105 C TA = 125 C 1. No floating I/Os 2. Based on characterization results, unless otherwise specified 3. Timer 2 clock enabled and counter running 64/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters Table 20. Symbol Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V (1)(2) Parameter Conditions TA = -40 C to 25 C TA = 55 C all peripherals OFF TA = 85 C TA = 105 C LSI RC osc. (at 38 kHz) TA = 125 C TA = -40 C to 25 C TA = 55 C with TIM2 active(3) TA = 85 C TA = 105 C Typ Max Unit 3 TBD 4.4 6.7 11 3.4 TBD 4.8 7 11.3 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A IDD(LPW) Supply current in Low power wait mode TA = 125 C TA = -40 C to 25 C TA = 55 C all peripherals OFF TA = 85 C TA = 105 C LSE external clock (32.768 kHz) TA = 125 C TA = -40 C to 25 C TA = 55 C with TIM2 active (3) TA = 85 C TA = 105 C TA = 125 C 1. No floating I/Os. 2. Based on characterization results, unless otherwise specified. 3. Timer 2 clock enabled and counter running. Doc ID 15962 Rev 2 65/101 Electrical parameters Table 21. Symbol STM8L151xx, STM8L152xx Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V (1)(2) Parameter Conditions TA = -40 C to 25 C TA = 55 C LCD OFF TA = 85 C TA = 105 C TA = 125 C TA = -40 C to 25 C LSI RC (at 38 kHz) LCD ON (static duty) (3) Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max Unit TA = 55 C TA = 85 C TA = 105 C TA = 125 C TA = -40 C to 25 C A TA = 55 C LCD ON T = 85 C (1/4 duty) (4) A TA = 105 C IDD(AH) Supply current in Active-halt mode TA = 125 C TA = -40 C to 25 C TA = 55 C LCD OFF TA = 85 C TA = 105 C TA = 125 C TA = -40 C to 25 C LSE external clock (32.768 kHz) LCD ON (static duty) (3) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A TA = 55 C TA = 85 C TA = 105 C TA = 125 C TA = -40 C to 25 C TA = 55 C LCD ON T = 85 C (1/4 duty) (4) A TA = 105 C TA = 125 C IDD(WUFAH) Supply current during wakeup time from Active-halt mode (using HSI) TBD mA 66/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 21. Symbol Electrical parameters Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V (1)(2) (continued) Parameter Conditions Typ 5 Max TBD Unit s Wakeup time from tWU_HSI(AH)(5)(6) Active-halt mode to Run mode (using HSI) Wakeup time from tWU_LSI(AH)(5)(6) Active-halt mode to Run mode (using LSI) 1. No floating I/O, unless otherwise specified. 2. Based on characterization results, unless otherwise specified. 3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected. TBD TBD s 4. LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 5. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU. 6. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register. Table 22. Total current consumption and timing in Halt mode at VDD = 2 V (1)(2) Parameter Condition TA = -40 C to 25 C Typ 400 TBD TBD TBD TBD Max TBD TBD(3) nA TBD TBD(3) mA Unit Symbol IDD(Halt) Supply current in Halt mode (Ultra low power ULP bit =1 in the PWR_CSR2 register) TA = 55 C TA = 85 C TA = 105 C IDD(WUHalt) tWU_HSI(Halt)(4)(5) tWU_LSI(Halt) (4)(5) Supply current during wakeup time from Halt mode (using HSI) Wakeup time from Halt to Run mode (using HSI) Wakeup time from Halt mode to Run mode (using LSI) 5 TBD TBD TBD s s 1. TA = -40 to 125 C, no floating I/O, unless otherwise specified 2. Based on characterization results, unless otherwise specified 3. Tested in production 4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register 5. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU Doc ID 15962 Rev 2 67/101 Electrical parameters STM8L151xx, STM8L152xx Current consumption of on-chip peripherals Table 23. Symbol IDD(TIM1) IDD(TIM2) IDD(TIM3) IDD(TIM4) IDD(USART1) IDD(SPI1) IDD(I2C1) IDD(DMA1) IDD(WWDG) IDD(ALL) IDD(RTC) Peripheral current consumption Parameter TIM1 supply current(1) TIM2 supply current (1) TIM3 supply current (1) TIM4 timer supply current (1) USART1 supply current (2) SPI1 supply current (2) I2C1 supply current (2) DMA1 supply current WWDG supply current Peripherals ON(3) RTC supply current when clocked by LSI RTC supply current when clocked at 1 MHz LCD supply current when clocked at 32 kHz /2 LCD supply current when clocked at 1 MHz /2 ADC1 supply current(4) DAC supply current(5) Comparator 1 supply current(6) Comparator 2 supply current(6) Slow mode Fast mode Typ. VDD = 3.0 V 13 8 8 3 6 3 5 3 2 44 TBD TBD A TBD TBD 1500 370 0.160 2 5 2.8 TBD A A/MHz A/MHz Unit IDD(LCD) IDD(ADC1) IDD(DAC) IDD(COMP1) IDD(COMP2) IDD(PVD/BOR) IDD(IDWDG) Power voltage detector and brownout Reset unit supply current (7) Independent watchdog supply current 1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production. 2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in wait mode in both cases. No I/O pins toggling. Not tested in production. 3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion. 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD /2. DAC output is in high-impedance. 6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs. Supply current of internal reference voltage excluded. 7. Including supply current of internal reference voltage. 68/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8.3.4 Clock and timing characteristics HSE external clock (HSEBYP = 1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 24. Symbol fHSE_ext VHSEH(2) VHSEL(2) Cin(HSE) ILEAK_HSE HSE external clock characteristics Parameter External clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN input capacitance(1) OSC_IN input leakage current VSS < VIN < VDD TBD Conditions Min 1 0.7 x VDD VSS TBD TBD Typ Max 16 TBD V 0.3 x VDD pF nA Unit MHz 1. Guarenteed by design, not tested in production. 2. Data based on characterization results, not tested in production. LSE external clock (LSEBYP=1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 25. Symbol fLSE_ext VLSEH(2) VLSEL(2) Cin(HSE) ILEAK_HSE LSE external clock characteristics Parameter External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN input capacitance(1) OSC32_IN input leakage current TBD Min 1 0.7 x VDD VSS TBD TBD Typ 32.768 Max TBD TBD V 0.3 x VDD pF nA Unit kHz 1. Guarenteed by design, not tested in production. 2. Data based on characterization results, not tested in production. Doc ID 15962 Rev 2 69/101 Electrical parameters STM8L151xx, STM8L152xx HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 26. Symbol fHSE RF C(1) HSE oscillator characteristics Parameter High speed external oscillator frequency Feedback resistor Recommended load capacitance (2) C = 20 pF, fOSC = 16 MHz C = 10 pF, fOSC =16 MHz Oscillator transconductance VDD is stabilized 3.5 1 Conditions Min 1 TBD TBD TBD (startup) TBD (stabilized)(3) mA TBD (startup) TBD (stabilized)(3) mA/V ms Typ Max 16 Unit MHz k pF IDD(HSE) HSE oscillator power consumption gm tSU(HSE)(4) Startup time 1. C=CL1=CL2 is approximately equivalent to 2 x crystal Cload. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. Data based on characterization results, not tested in production. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 12. HSE oscillator circuit diagram Rm Lm Cm Resonator Consumption control CO CL1 OSC_IN gm RF fHSE to core Resonator STM8 OSC_OUT CL2 HSE oscillator critical gm formula g mcrit = ( 2 x x f HSE ) 2 x R m ( 2Co + C ) 2 Rm: Notional resistance (see crystal specification), Lm: Notional inductance (see crystal specification), Cm: Notional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification), CL1=CL2=C: Grounded external capacitance gm >> gmcrit 70/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 27. Symbol fLSE RF C(1) IDD(LSE) gm tSU(LSE)(4) LSE oscillator characteristics Parameter Low speed external oscillator frequency Feedback resistor Recommended load capacitance (2) LSE oscillator power consumption Oscillator transconductance Startup time VDD is stabilized TBD Conditions Min Typ 32.768 TBD TBD TBD(3) Max Unit kHz k pF A A/V ms 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value. Refer to crystal manufacturer for more details 3. Data based on characterization results, not tested in production. 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 13. LSE oscillator circuit diagram Rm Lm Cm Resonator Consumption control CO CL1 OSC_IN gm RF fLSE Resonator STM8 OSC_OUT CL2 Doc ID 15962 Rev 2 71/101 Electrical parameters STM8L151xx, STM8L152xx Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) Table 28. Symbol fHSI HSI oscillator characteristics (1) Parameter Frequency VDD = 3.0 V VDD = 3.0 V, TA = 25 C VDD = 3.0 V, 0 C TA 55 C VDD = 3.0 V, -10 C TA 70 C VDD = 3.0 V, -10 C TA 85 C VDD = 3.0 V, -10 C TA 125 C 1.65 V VDD 3.6 V, -40 C TA 125 C -1 (2) Conditions Min Typ 16 Max Unit MHz 1 (2) % % % % % % % -1.5 (2) -2 (2) (2) (2) 1.5 (2) 2 (2) ACCHSI Accuracy of HSI oscillator (factory calibrated) -2.5 -4.5 2(2) 2 (2) -4.5 0.4 (2) 3.7 100 3 0.5 7.4 (2) 140 (2) TRIM tsu(HSI) IDD(HSI) HSI user trim resolution HSI oscillator setup time (wakeup time) HSI oscillator power consumption 1.65 V VDD 3.6 V, -40 C TA 125 C s A 1. VDD = 3.0 V, TA = -40 to 125 C unless otherwise specified. 2. Data based on characterization results, not tested in production. Low speed internal RC oscillator (LSI) Table 29. Symbol fLSI tsu(LSI) IDD(LSI) LSI oscillator characteristics (1) Parameter Frequency LSI oscillator wakeup time LSI oscillator frequency drift(3) 0 C TA 85 C -10 Conditions Min 26 Typ 38 TBD Max 56 TBD(2) 4 Unit kHz s % 1. VDD = 1.8 V to 3.0 V, TA = -40 to 125 C unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. This is a deviation for an individual part, once the initial frequency has been measured. 72/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8.3.5 Memory characteristics TA = -40 to 125 C unless otherwise specified. Table 30. Symbol VRM RAM and hardware registers Parameter Data retention mode (1) Conditions Halt mode (or Reset) Min 1.4 Typ Max Unit V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 31. Symbol VDD Flash program memory Parameter Operating voltage (all modes, read/write/erase) Programming time for 1 or 128 bytes (block) erase/write cycles (on programmed byte) Conditions fSYSCLK = 16 MHz Min 1.65 Typ Max (1) Unit V ms ms 3.6 TBD TBD tprog Programming time for 1 to 128 bytes (block) write cycles (on erased byte) Programming/ erasing consumption Data retention (program memory) after 10000 erase/write cycles at TA=+85 C TA=+25 C, VDD = 3.0 V TA=+25 C, VDD = 1.8 V TRET=+55 C TRET=+55 C TRET=+85 C See notes (1)(2) See notes (1)(3) TBD(1) TBD(1) TBD(1) TBD(1) TBD(1) (4) TBD mA TBD Iprog tRET Data retention (data memory) after 10000 erase/write cycles at TA=+85 C Data retention (data memory) after 10000 erase/write cycles at TA=+85 C Erase/write cycles (program memory) years NRW kcycles Erase/write cycles (data memory) 1. Data based on characterization results, not tested in production. 2. Retention guaranteed after cycling is 10 years @ 55 C. 3. Retention guaranteed after cycling is 1 year @ 55 C. 4. Data based on characterization performed on the whole data memory. Doc ID 15962 Rev 2 73/101 Electrical parameters STM8L151xx, STM8L152xx 8.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 32. Symbol I/O static characteristics (1) Parameter Conditions Input voltage on true open-drain pins (PC0 and PC1) Min VSS -0.3 Typ Max 0.3 x VDD V Unit VIL Input low level voltage(2) Input voltage on FT pins (PA7 and PE0) Input voltage on any other pin Input voltage on true open-drain pins (PC0 and PC1) VSS -0.3 VSS -0.3 0.3 x VDD 0.3 x VDD 0.70 x VDD VDD+3.6 V VIH Input high level voltage (2) Input voltage on FT pins (PA7 and PE0) Input voltage on any other pin 0.70 x VDD 0.70 x VDD 200 VDD+3.6 VDDmax+0.3 Vhys Schmitt trigger voltage hysteresis (3) Standard I/Os True open drain I/Os VSSVINVDD Standard I/Os - mV 250 50 (5) 200(5) Ilkg Input leakage current (4) VSSVINVDD True open drain I/Os VSSVINVDD PA0 with high sink LED driver capability nA 30 45 5 200(5) 60 k pF RPU CIO(7) Weak pull-up equivalent resistor(6) I/O pin capacitance VIN=VSS 1. VDD = 3.0 V, TA = -40 to 125 C unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 6. RPU pull-up equivalent resistor based on a resistive transistor. 7. Data guaranteed by Design, not tested in production. 74/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 33. Output driving current (standard ports) Parameter Conditions IIO = +2 mA, VDD = 3.0 V VOL (1) Standard Output low level voltage for an I/O pin IIO = +2 mA, VDD = 1.8 V IIO = +10 mA, VDD = 3.0 V IIO = -2 mA, VDD = 3.0 V VOH (2) Output high level voltage for an I/O pin IIO = -1 mA, VDD = 1.8 V IIO = -10 mA, VDD = 3.0 V VDD-0.45 VDD-0.45 VDD-0.7 Min Max Unit I/O Symbol Type 0.45 V 0.45 V 0.7 V V V V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Table 34. Output driving current (true open drain ports) Parameter Conditions IIO = +3 mA, VDD = 3.0 V IIO = +1 mA, VDD = 1.8 V Min Max Unit I/O Symbol Type Open drain 0.45 VOL (1) Output low level voltage for an I/O pin 0.45 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Table 35. Output driving current (PA0 with high sink LED driver capability) Parameter Conditions IIO = +20 mA, VDD = 2.0 V Min Max Unit I/O Symbol Type VOL (1) IR Output low level voltage for an I/O pin TBD 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Doc ID 15962 Rev 2 75/101 Electrical parameters STM8L151xx, STM8L152xx NRST pin Subject to general operating conditions for VDD and TA unless otherwise specified. Table 36. Symbol VIL(NRST) VIH(NRST) VOL(NRST) RPU(NRST) VF(NRST) VNF(NRST) NRST pin characteristics Parameter NRST Input low level voltage (1) NRST Input high level voltage (1) NRST Output low level voltage NRST Pull-up equivalent resistor (2) NRST Input filtered pulse (3) NRST Input not filtered pulse (3) 300 IOL = 2 mA 30 45 Conditions Min VSS 1.4 Typ (1) Max 0.8 VDD VDD-0.8 60 50 ns k V Unit 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor 3. Data guaranteed by design, not tested in production. The reset network shown in Figure 14 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 36. Otherwise the reset is not taken into account internally. Figure 14. Recommended NRST pin configuration VDD RPU EXTERNAL RESET CIRCUIT 0.01 F RSTIN Filter INTERNAL RESET STM8L 76/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8.3.7 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 37. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS) (2) (2) SPI1 characteristics Parameter SPI clock frequency Slave mode SPI clock rise and fall time Capacitive load: C = 30 pF NSS setup time NSS hold time SCK high and low time Slave mode Slave mode Master mode, fSYSCLK = 8 MHz, fSCK= 4 MHz Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Data output disable time Data output valid time Data output valid time Slave mode Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Data output hold time Master mode (after enable edge) TBD TBD TBD TBD 3x 1/fSYSCLK TBD TBD TBD TBD ns 0 4 x 1/fSYSCLK TBD TBD TBD 8 TBD TBD Conditions(1) Master mode Min 0 Max 8 MHz Unit tw(SCKH) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI) (2) th(SI)(2) ta(SO)(2)(3) tdis(SO)(2)(4) tv(SO) (2) tv(MO)(2) th(SO)(2) th(MO)(2) 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Doc ID 15962 Rev 2 77/101 Electrical parameters Figure 15. SPI timing diagram - slave mode and CPHA=0 STM8L151xx, STM8L152xx NSS input tSU(NSS) tc(SCK) th(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT ta(SO) MISO OUT P UT MOSI I NPUT th(SO) BI T6 OUT tdis(SO) M SB IN th(SI) B I T1 IN LSB IN ai14134 Figure 16. SPI timing diagram - slave mode and CPHA=1(1) NSS input tSU(NSS) tc(SCK) th(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 78/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Figure 17. SPI timing diagram - master mode(1) High NSS input tc(SCK) Electrical parameters SCK Input SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15962 Rev 2 79/101 Electrical parameters STM8L151xx, STM8L152xx I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 38. I2C characteristics Standard mode I2C Min(2) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time 4.7 4.0 250 0 1000 Max (2) Fast mode I2C(1) Unit Min (2) 1.3 0.6 100 0 900 300 ns Max (2) s Symbol Parameter SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time STOP to START condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 300 0.6 0.6 0.6 1.3 400 300 s s s 400 pF 1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. Note: For speeds around 200 kHz, the achieved speed can have a 5% tolerance For other speed ranges, the achieved speed can have a 2% tolerance The above variations depend on the accuracy of the external components used. 80/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters Figure 18. Typical application with I2C bus and timing diagram 1) VDD 4.7k I2C BUS 4.7k VDD 100 100 SDA SCL STM8L REPEATED START START tsu(STA) SDA tw(STO:STA) START tf(SDA) SCL tr(SDA) tsu(SDA) th(SDA) STOP th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 8.3.8 LCD controller (STM8L152xx only) Table 39. Symbol VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD5 VLCD6 VLCD7 Cext IDD RH RL V33 V23 V12 V13 V0 LCD characteristics(1) Parameter LCD external voltage LCD internal reference voltage 0 LCD internal reference voltage 1 LCD internal reference voltage 2 LCD internal reference voltage 3 LCD internal reference voltage 4 LCD internal reference voltage 5 LCD internal reference voltage 6 LCD internal reference voltage 7 VLCD external capacitance Supply current(2) at VDD = 1.8 V Supply current(2) at VDD = 3 V Low drive resistive network High drive resistive network Segment/Common higher level voltage Segment/Common 2/3 level voltage Segment/Common 1/2 level voltage Segment/Common 1/3 level voltage Segment/Common lowest level voltage 0 2/3VLCDx 1/2VLCDx 1/3VLCDx 0.1 TBD TBD TBD TBD VLCDx M k V V V V V 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2 Min Typ Max. 3.6 Unit V V V V V V V V V F 1. Data guaranteed by Design, not tested in production. 2. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels active, no LCD connected. Doc ID 15962 Rev 2 81/101 Electrical parameters STM8L151xx, STM8L152xx VLCD external capacitor (STM8L152xx only) The application can achieve a stabilized LCD reference voltage by connecting an external capacitor CEXT to the VLCD pin. CEXT is specified in Table 39. 8.3.9 Table 40. Symbol IREFINT Embedded reference voltage Reference voltage characteristics(1) Parameter Internal reference voltage consumption ADC sampling time when reading the internal reference voltage(2) Internal reference voltage buffer consumption (used for ADC) Reference voltage output 1/4 reference voltage 1/2 reference voltage 3/4 reference voltage Internal reference voltage low power buffer consumption (used for comparators or output) Buffer ouptut current(3) Reference voltage output load Internal reference voltage startup time Internal reference voltage buffer startup time once enabled (2) Accuracy of VREFINT stored in engibyte Stability of VREFINT in temperature Stability of VREFINT after 1000 hours 20 2 TBD Min Typ 1.4 5 13.5 1.225 25 50 75 730 1200 1 50 TBD 10 5 50 TBD nA A pF ms s mV ppm/C ppm %VREFINT_COMP 10 25 TBD Max. Unit A s A V TS_VREFINT IBUF VREFINT out VREFINT_DIV1 VREFNT_DIV2 VREFNT_DIV3 ILPBUF IREFOUT CREFOUT tVREFINT tBUFEN ACCVREFINT STABVREFINT STABVREFINT 1. Based on characterization results, unless otherwise specified 2. Defined when ADC output reaches its final value 1/2LSB 3. To guaranty less than 1% VREFOUT deviation 8.3.10 Temperature sensor Table 41. Symbol V25 TL Avg_slope IDD(TEMP) TS characteristics(1) Parameter Sensor reference voltage at 25C VSENSOR linearity with temperature Average slope Consumption TBD Min TBD Typ 0.495 TBD TBD 3.4 Max. TBD TBD TBD 6 Unit V C mV/C A 82/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 41. Symbol TSTART TS_TEMP Electrical parameters TS characteristics(1) (continued) Parameter Temperature sensor startup time (2) Min Typ Max. 10 Unit s s ADC sampling time when reading the temperature sensor 5 10 1. Based on characterization results, unless otherwise specified. 2. Defined for ADC output reaches its final value 1/2LSB. 8.3.11 Comparator characteristics Table 42. Comparator 1 characteristics Parameter Analog supply voltage Temperature range R400 value Error on R400 R10 value Error on R10 Comparator input voltage range Internal reference reference voltage Startup time after enable Propagation delay(2) Comparator offset error Consumption(3) TBD 0 TBD 1.225 7 3 3 160 TBD 10 Min (1) 1.65 -40 TBD 400 Typ Max(1) 3.6 125 TBD TBD TBD TBD VDDA TBD TBD TBD TBD TBD s s mV nA Unit V C k % k % V Symbol VDDA TA R400 Err400 R10 Err10 VIN VREFINT tSTART td Voffset ICMP1 1. Data guaranteed by design, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Table 43. Symbol VDDA TA VIN Comparator 2 characteristics Parameter Analog supply voltage Temperature range Comparator input voltage range Startup time after enable in fast mode 1.65 V to 2.7 V 2.7 V to 3.6 V 1.65 V to 2.7 V 2.7 V to 3.6 V Conditions Min (1) 1.65 -40 0 Typ Max(1) 3.6 125 VDDA TBD s TBD TBD s TBD Unit V C V tSTART Startup time after enable in slow mode Doc ID 15962 Rev 2 83/101 Electrical parameters Table 43. Symbol tdf STM8L151xx, STM8L152xx Comparator 2 characteristics Parameter Propagation delay in fast mode(2) Propagation delay in slow mode(2) Comparator offset error 2.7 V to 3.6 V 1.65 V to 2.7 V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A A Conditions 1.65 V to 2.7 V 2.7 V to 3.6 V 1.65 V to 2.7 V 2.7 V to 3.6 V 1.65 V to 2.7 V Min (1) Typ TBD TBD TBD TBD TBD Max(1) TBD TBD TBD TBD TBD mV s Unit s tds Voffset IDD(CMP2F) Consumption in fast mode 2.7 V to 3.6 V 1.65 V to 2.7 V IDD(CMP2S) Consumption in slow mode 2.7 V to 3.6 V 1. Data guaranteed by design, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 8.3.12 Table 44. Symbol VDDA VREF+ TA 12-bit DAC characteristics DAC characteristics, output on PF0(1) Parameter Analog supply voltage Reference supply voltage Temperature range No load, middle code 0x800 on the inputs Conditions Min (2) 1.8 1.8 -40 370 Typ Max(1) 3.6 3.6 125 TBD A Unit V V C IVDDA Current on VDDA supply No load, worst code 0xF1C @ VREF+=3.6V on the inputs 500 210 TBD TBD IVREF+ RL RO CL DAC_OUT Current on VREF+ supply Resistive load (3) DACOUT buffer ON DACOUT buffer OFF 5 TBD 50 k k pF V V Output impedance Capacitive load(4) DAC_OUT voltage(5) DACOUT buffer ON DACOUT buffer OFF RL 5 k, CL50 pF DACOUT buffer ON CL50 pF DACOUT buffer OFF 0.2 0 1 TBD VREF+-0.2 VREF+ TBD DNL Differential non linearity(6) 12-bit LSB TBD 84/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 44. Symbol Electrical parameters DAC characteristics, output on PF0(1) (continued) Parameter Conditions RL 5 k, CL 50 pF DACOUT buffer ON CL 50 pF Min (2) Typ 2 TBD 20 TBD 0.5 TBD TBD TBD Max(1) TBD TBD TBD Unit INL Integral non linearity(7) DACOUT buffer OFF RL 5 k, CL 50 pF DACOUT buffer ON CL 50 pF 12-bit LSB Offset Offset error(8) mV TBD TBD % TBD TBD 12-bit LSB TBD DACOUT buffer OFF RL 5 k, CL 50 pF DACOUT buffer ON Gain error Gain error CL 50 pF DACOUT buffer OFF RL 5 k, CL 50 pF DACOUT buffer ON TUE Total unadjusted error CL 50 pF DACOUT buffer OFF tsettling Settling time (full scale: for a 12bit input code transition between the lowest and the highest input codes when DAC_OUT reaches the final value 1LSB Max frequency for a correct DAC_OUT (@95%) change when small variation of the input code (from code i to i+1LSB). Wakeup time from OFF state. Input code between lowest and highest possible codes. Power supply rejection ratio (to VDDA) (static DC measurement) RL 5 k, CL 50 pF 7 TBD s Update rate RL 5 k, CL 50 pF 1 Msps tWAKEUP RL 5 k, CL50 pF RL 5 k, CL50 pF 9 TBD s PSRR+ -60 -35 dB 1. For 48-pin package only. 2. Data guaranteed by design, not tested in production. 3. Resistive load between DACOUT and GNDA. 4. Capacitive load at DACOUT pin. 5. It gives the output excursion of the DAC. 6. Difference between two consecutive codes - 1 LSB. 7. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023. 8. Difference between measured value and ideal value=VREF/2. Doc ID 15962 Rev 2 85/101 Electrical parameters Table 45. DAC output on PB4-PB5-PB6(1) Parameter Internal resistance between DAC output and PB4-PB5-PB6 output Min (2) STM8L151xx, STM8L152xx Symbol Rint Typ TBD Max(1) TBD Unit k 1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing interface I/O switch registers. 2. Data guaranteed by design, not tested in production. 86/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters 8.3.13 Table 46. Symbol VDDA VREF+ VREFIVDDA IVREF+ VAIN TA RAIN RADC 12-bit ADC1 characteristics ADC1 characteristics Parameter Analog supply voltage Reference supply voltage Lower reference voltage Current on the VDDA input pin Current on the VREF+ input pin Conversion voltage range Temperature range External resistance on VAIN on PF0 fast channel Sampling switch resistance on all other channels on PF0 fast channel Internal sample and hold capacitor on all other channels 2.4 VVDDA3.6 V without zooming ADC sampling clock frequency 1.8 VVDDA2.4 V with zooming VAIN on PF0 fast channel Sampling rate VAIN on all other channels External trigger frequency External trigger latency VAIN on fast channel PF0 VAIN on slow channels 4(4) TBD 12 + tS 16 MHz Wakeup time from OFF state Internal reference voltage startup time 1(3) 3 refer to Table 40 TBD TBD 1/fADC 1/fADC 1/fADC 1/fADC 1/fADC s s ms 0.320 0.320 0.02 TBD 16 8 1(4) pF MHz MHz MHz TBD TBD k pF 0(2) -40 2.4 V VDDA 3.6 V 1.8 VVDDA 2.4 V Conditions Min (1) 1.8 2.4 VDDA VSSA 1000 400 TBD VREF+ 125 TBD(3) TBD C k k Typ Max(1) 3.6 VDDA Unit V V V V A A CADC fADC fS fTRIG tLAT tS Sampling time tconv tWKUP tVREFINT Conversion time 1. Data guaranteed by design, not tested in production. 2. VREF- or VDDA must be tied to ground. 3. For 1 Msps, maximum Rext is 0.5 k. 4. Value obtained for continous conversion on fast channel. Doc ID 15962 Rev 2 87/101 Electrical parameters Table 47. ADC1 accuracy Parameter Differential non linearity Integral non linearity Total unadjusted error Offset error Gain error Effective number of bits Signal-to-noise and distortion ratio Signal-to-noise ratio Total harmonic distorsion STM8L151xx, STM8L152xx Symbol DNL INL TUE Offset Gain ENOB SINAD SNR THD Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD Max(1) 1 2 5 2 3.5 9.5 TBD TBD TBD Unit LSB LSB LSB LSB LSB Bits dB dB dB 1. Data based on characterization, not tested in production. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 19 or Figure 20, depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. Figure 19. Power supply and reference decoupling (VREF+ not connected to VDDA) STM8L V REF+ 1 F // 10 nF V DDA 1 F // 10 nF V SSA/V REF- ai17031 88/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Electrical parameters Figure 20. Power supply and reference decoupling (VREF+ connected to VDDA) STM8L VREF+/VDDA 1 F // 10 nF VREF-/VSSA ai17032 8.3.14 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Doc ID 15962 Rev 2 89/101 Electrical parameters Table 48. Symbol STM8L151xx, STM8L152xx EMS data Parameter Conditions Level/ Class VFESD VDD = 3.3 V, TA = +25 C, Voltage limits to be applied on any I/O pin to fCPU= 16 MHz, induce a functional disturbance conforms to IEC 61000 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 C, fCPU = 16 MHz, conforms to IEC 61000 TBD VEFTB TBD Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC61967-2 which specifies the board and the loading of each pin. Table 49. Symbol EMI data (1) Parameter Conditions Monitored frequency band 0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level Max vs. Unit 16 MHz TBD TBD TBD 1 dBV SEMI Peak level VDD = 3.6 V, TA = +25 C, LQFP32 conforming to IEC61967-2 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the JESD22-A114A/A115A standard. 90/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Table 50. Symbol VESD(HBM) VESD(CDM) Electrical parameters ESD absolute maximum ratings Ratings Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Conditions Maximum value (1) 2000 TA = +25 C 1000 V Unit 1. Data based on characterization results, not tested in production. Static latch-up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical sensitivities Parameter Static latch-up class Class II Table 51. Symbol LU 8.4 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 58. The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C JA is the package junction-to-ambient thermal resistance in C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Doc ID 15962 Rev 2 91/101 Electrical parameters Table 52. Symbol JA JA JA JA JA STM8L151xx, STM8L152xx Thermal characteristics(1) Parameter Thermal resistance junction-ambient WFQFPN28 - 4 x 4 mm Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm Thermal resistance junction-ambient VFQFPN 32 - 5 x 5 mm Thermal resistance junction-ambient LQFP 48- 7 x 7 mm Thermal resistance junction-ambient VFQFPN 48- 7 x 7mm Value TBD TBD TBD TBD TBD Unit C/W C/W C/W C/W C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 92/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Package characteristics 9 9.1 Package characteristics ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 15962 Rev 2 93/101 Package characteristics STM8L151xx, STM8L152xx 9.2 Package mechanical data Figure 22. Recommended footprint (dimensions in mm)(1) Figure 21. WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4)(1) A A3 D e 7 14 15 A1 ddd b e E 1 L2 28 22 21 L1 DG_ME b 1. Drawing is not to scale. Table 53. WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data(1) mm inches(2) Max 0.8 0.05 Min 0.0276 0 Typ 0.0295 0.0008 0.0079 0.3 0.0071 0.0098 0.1575 0.1575 0.0197 0.45 0.5 0.0098 0.0118 0.0138 0.0157 0.0031 Number of pins 0.0177 0.0197 0.0118 Max 0.0315 0.002 Dim. Min A(1) A1 A3 b D E e L1 L2 ddd 0.25 0.3 0.18 0.7 0 Typ 0.75 0.02 0.2 0.25 4 4 0.5 0.35 0.4 0.08 N 28 1. Thickness valid for the WFQFPN28 package in the sampling phase. In the production phase, the UFQFPN28 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 94/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Package characteristics Figure 23. WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) Seating plane C A ddd C A3 A1 D e 9 8 16 17 E2 b E 1 32 24 L Pin # 1 ID R = 0.30 D2 Bottom view L A0A3_ME 1. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS. Table 54. WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data(1) mm inches(2) Max 0.80 0.05 Min 0.0276 Typ 0.0295 0.0008 0.0079 0.30 5.15 3.70 5.15 3.70 0.0071 0.1909 0.1260 0.1909 0.1260 0.0098 0.1969 0.1358 0.1969 0.1358 0.0197 0.50 0.0118 0.0157 0.0031 Number of pins 0.0197 0.0118 0.2028 0.1457 0.2028 0.1457 Max 0.0315 0.0020 Dim. Min A(1) A1 A3 b D D2 E E2 e L ddd 0.30 0.18 4.85 3.20 4.85 3.20 0.70 0 Typ 0.75 0.02 0.20 0.25 5.00 3.45 5.00 3.45 0.50 0.40 0.08 N 32 1. Thickness valid for the WFQFPN32 package in the sampling phase. In the production phase, the UFQFPN32 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15962 Rev 2 95/101 Package characteristics STM8L151xx, STM8L152xx Figure 24. LQFP32 - 32-pin low profile quad flat package outline ccc C D D1 D3 24 25 b E3 32 Pin 1 identification E1 E 17 16 L1 A A2 9 A1 1 8 L K c 5V_ME Table 55. Dim. LQFP32 - 32-pin low profile quad flat package, package mechanical data mm Min Typ Max 1.6 0.05 1.35 0.3 0.09 8.8 6.8 9 7 5.6 8.8 6.8 9 7 5.6 0.8 0.45 0.6 1 0.0 3.5 0.1 Number of pins 7.0 0.0 0.75 0.0177 9.2 7.2 0.3465 0.2677 1.4 0.37 0.15 1.45 0.45 0.2 9.2 7.2 0.0020 0.0531 0.0118 0.0035 0.3465 0.2677 0.3543 0.2756 0.2205 0.3543 0.2756 0.2205 0.0315 0.0236 0.0394 3.5 0.0039 7.0 0.0295 0.3622 0.2835 0.0551 0.0146 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0177 0.0079 0.3622 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc N 32 1. Values in inches are converted from mm and rounded to 4 decimal digits. 96/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Package characteristics Figure 25. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 26. Recommended footprint outline(1)(2) (dimensions in mm)(1) D2 L 13 12 b 24 25 48 1 7.30 37 36 L E e b E2 7.30 0.20 6.20 6.20 5.60 5.80 1 48 37 36 0.30 5.60 e D A A1 A3 0.55 12 13 24 25 5.80 0.50 0.75 ai15697 C A2 Seating plane V0_ME 1. Drawing is not to scale. 2. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS. Table 56. VFQFPN48 - very thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data(1) millimeters inches(2) Max 1.000 0.050 1.000 Typ 0.0354 0.0008 0.0256 0.0098 0.180 6.850 2.250 6.850 2.250 0.450 0.300 0.080 0.300 7.150 5.250 7.150 5.250 0.550 0.500 0.0091 0.2756 0.1850 0.2756 0.1850 0.0197 0.0157 0.0071 0.2697 0.0886 0.2697 0.0886 0.0177 0.0118 0.0031 0.0118 0.2815 0.2067 0.2815 0.2067 0.0217 0.0197 Min 0.0315 Max 0.0394 0.0020 0.0394 Symbol Typ A(1) A1 A2 A3 b D D2 E E2 e L ddd 0.900 0.020 0.650 0.250 0.230 7.000 4.700 7.000 4.700 0.500 0.400 Min 0.800 1. Thickness valid for the VFQFPN48 package in the sampling phase. In the production phase, the UFQFPN48 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15962 Rev 2 97/101 Package characteristics STM8L151xx, STM8L152xx Figure 27. LQFP48 - 48-pin low profile quad flat package outline (7x7) D D1 D3 36 37 b E3 E1 E 25 24 L1 ccc C A A2 48 Pin 1 identification 13 1 12 A1 L K c 5B_ME Table 57. Dim. LQFP48 - 48-pin low profile quad flat package (7x7), package mechanical data mm Min Typ Max 1.6 0.05 1.35 0.17 0.09 8.8 6.8 9 7 5.5 8.8 6.8 9 7 5.5 0.5 0.45 0.6 1 0.0 3.5 7.0 0.08 Number of pins 0.0 0.75 0.0177 9.2 7.2 0.3465 0.2677 1.4 0.22 0.15 1.45 0.27 0.2 9.2 7.2 0.002 0.0531 0.0067 0.0035 0.3465 0.2677 0.3543 0.2756 0.2165 0.3543 0.2756 0.2165 0.0197 0.0236 0.0394 3.5 7.0 0.0031 0.0295 0.3622 0.2835 0.0551 0.0087 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0106 0.0079 0.3622 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc N 48 1. Values in inches are converted from mm and rounded to 4 decimal digits. 98/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Device ordering information 10 Device ordering information Figure 28. STM8L15xxx ordering information scheme Example: STM8 L 151 C 4 U 6 Product class STM8 microcontroller Family type L = Low power Sub-family type 151 = Ultralow power 152 = Ultralow power with LCD Pin count C = 48 pins K = 32 pins G = 28 pins Program memory size 4 = 16 Kbytes 6 = 32 Kbytes Package U = WFQFPN or VFQFPN T = LQFP Temperature range 3 = - 40 C to 125 C 6 = - 40 C to 85 C For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST sales office nearest to you. Doc ID 15962 Rev 2 99/101 Revision history STM8L151xx, STM8L152xx 11 Revision history Table 58. Date 06-Aug-2009 Document revision history Revision 1 Initial release Updated peripheral naming throughout document. Added Figure 6: STM8L151Cx 48-pin pinout (without LCD) on page 24 Added capacitive sensing channels in Features on page 1 Updated PA7, PC0 and PC1 in Table 4: STM8L15x pin description Changed CLK and REMAP register names in Table 7 Changed description of WDGHALT in Table 11 Added typical power consumption values in Table 16 to Table 23 Correct VIH max in Table 32 Changes 10-Sep-2009 2 100/101 Doc ID 15962 Rev 2 STM8L151xx, STM8L152xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15962 Rev 2 101/101 |
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